/external/llvm/test/MC/AArch64/ |
D | arm64-arithmetic-encoding.s | 172 add w1, w2, w3, uxtw 181 ; CHECK: add w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x0b] 190 add x1, x2, w3, uxtw 197 ; CHECK: add x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x8b] 203 add w1, wsp, w3, uxtw #0 216 sub w1, w2, w3, uxtw 225 ; CHECK: sub w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x4b] 234 sub x1, x2, w3, uxtw 241 ; CHECK: sub x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xcb] 247 sub w1, wsp, w3, uxtw #0 [all …]
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D | arm64-aliases.s | 91 cmp x8, w8, uxtw 92 cmp w9, w8, uxtw 104 ; CHECK: cmp x8, w8, uxtw ; encoding: [0x1f,0x41,0x28,0xeb] 105 ; CHECK: cmp w9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0x6b]
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D | basic-a64-instructions.s | 20 add x12, x1, w20, uxtw 38 add w30, w29, wzr, uxtw 56 add w17, w19, w23, uxtw #2 66 sub x12, x1, w20, uxtw 83 sub w30, w29, wzr, uxtw 101 adds x12, x1, w20, uxtw 118 adds w30, w29, wzr, uxtw 136 subs x12, x1, w20, uxtw 153 subs w30, w29, wzr, uxtw 171 cmp x1, w20, uxtw [all …]
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D | basic-a64-diagnostics.s | 847 uxtw x3, x5 2433 ldr w9, [x5, x5, uxtw] 2466 ldr h13, [x4, w2, uxtw #2] 2475 str s3, [sp, w9, uxtw #1] 2489 ldr d3, [x20, wzr, uxtw #4] 2501 ldr q10, [x20, w4, uxtw #2] 2502 str q21, [x20, w4, uxtw #5]
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D | arm64-memory.s | 429 str d1, [sp, w3, uxtw #3] 431 str q1, [sp, w3, uxtw #4] 434 ; CHECK: str d1, [sp, w3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc] 436 ; CHECK: str q1, [sp, w3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c]
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D | arm64-diags.s | 116 ; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-register-offset-addressing.ll | 34 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 50 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 71 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1] 85 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 105 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] 119 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] 138 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3]
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D | ldst-regoffset.ll | 34 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 62 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 90 ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #1] 114 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 142 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] 166 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 190 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3] 215 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] 242 ; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] 268 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] [all …]
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D | fast-isel-int-ext.ll | 11 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3] 33 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3] 80 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3] 102 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3] 197 ; CHECK-NOT: uxtw 308 ; CHECK-NOT: uxtw 423 ; CHECK-NOT: uxtw
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D | addsub_ext.ll | 274 ; N.b. we could probably check more here ("add w2, w3, w1, uxtw" for 287 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw 292 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2 317 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw 322 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
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D | fast-isel-addressing-modes.ll | 418 ; CHECK: ldrb {{w[0-9]+}}, [x1, w0, uxtw] 428 ; CHECK: ldrh {{w[0-9]+}}, [x1, w0, uxtw #1] 439 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2] 450 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3] 486 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2] 497 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2] 508 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
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D | arm64-ldxr-stxr.ll | 66 ; CHECK-NOT: uxtw 115 ; CHECK-NOT: uxtw 203 ; CHECK-NOT: uxtw 252 ; CHECK-NOT: uxtw
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D | arm64-addr-mode-folding.ll | 128 ; CHECK-NOT: , uxtw #2] 151 ; CHECK: , uxtw #2] 152 ; CHECK: , uxtw #2]
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D | fast-isel-int-ext2.ll | 67 ; CHECK-NOT: uxtw 208 ; CHECK-NOT: uxtw 353 ; CHECK-NOT: uxtw
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D | arm64-arith.ll | 127 ; CHECK: add x0, x1, w8, uxtw #3 139 ; CHECK: add x0, x1, w0, uxtw
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-arithmetic.txt | 191 # CHECK: add x1, x2, w3, uxtw 233 # CHECK: sub x1, x2, w3, uxtw 275 # CHECK: adds x1, x2, w3, uxtw 313 # CHECK: subs x1, x2, w3, uxtw 329 # CHECK: cmp x8, w8, uxtw 330 # CHECK: cmp w9, w8, uxtw
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D | arm64-memory.txt | 101 # CHECK: strb w0, [x0, w0, uxtw] 429 # CHECK: str h0, [x0, w0, uxtw] 431 # CHECK: str d1, [sp, w3, uxtw #3] 433 # CHECK: str q1, [sp, w3, uxtw #4]
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D | basic-a64-instructions.txt | 2535 # CHECK: ldrb w14, [x26, w6, uxtw] 2536 # CHECK: ldrsb w15, [x25, w7, uxtw] 2555 # CHECK: ldrh w14, [x26, w6, uxtw] 2556 # CHECK: ldrh w15, [x25, w7, uxtw] 2557 # CHECK: ldrsh w16, [x24, w8, uxtw #1] 2580 # CHECK: str w14, [x26, w6, uxtw] 2581 # CHECK: ldr w15, [x25, w7, uxtw] 2582 # CHECK: ldr w16, [x24, w8, uxtw #2] 2605 # CHECK: prfm pldl1keep, [x26, w6, uxtw] 2606 # CHECK: ldr x15, [x25, w7, uxtw] [all …]
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/external/libmpeg2/common/armv8/ |
D | impeg2_format_conv.s | 144 uxtw x8, w8 317 uxtw x8, w8
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/external/libjpeg-turbo/simd/ |
D | jsimd_arm64_neon.S | 216 uxtw x3, w3 818 uxtw x3, w3 1117 uxtw x3, w3 1306 uxtw x3, w3 1730 ldr Y, [INPUT_BUF0, INPUT_ROW, uxtw #3] 1731 ldr U, [INPUT_BUF1, INPUT_ROW, uxtw #3] 1733 ldr V, [INPUT_BUF2, INPUT_ROW, uxtw #3] 2061 ldr Y, [OUTPUT_BUF0, OUTPUT_ROW, uxtw #3] 2062 ldr U, [OUTPUT_BUF1, OUTPUT_ROW, uxtw #3] 2064 ldr V, [OUTPUT_BUF2, OUTPUT_ROW, uxtw #3] [all …]
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/external/v8/src/arm64/ |
D | macro-assembler-arm64-inl.h | 1239 uxtw(rd, rn); in Uxtw()
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D | assembler-arm64.h | 1229 void uxtw(const Register& rd, const Register& rn) { in uxtw() function
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/external/vixl/src/aarch64/ |
D | assembler-aarch64.h | 808 void uxtw(const Register& rd, const Register& rn) { ubfm(rd, rn, 0, 31); } in uxtw() function
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D | macro-assembler-aarch64.h | 2118 uxtw(rd, rn); in Uxtw()
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/external/valgrind/none/tests/arm64/ |
D | memory.stdout.exp | 945 str x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 975 str x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4 1125 ldr x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 1155 ldr x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4 1305 str w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 1335 str w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4 1485 ldr w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 1515 ldr w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4 1665 strh w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4 1695 strh w13, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4 [all …]
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