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Searched refs:v1i32 (Results 1 – 16 of 16) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.image.sample-masked.ll9 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
22 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
35 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
48 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
61 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
73 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
85 …%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, …
92 declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32…
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h87 v1i32 = 38, // 1 x i32 enumerator
235 SimpleTy == MVT::v1i32 || SimpleTy == MVT::v2f16 || in is32BitVector()
342 case v1i32: in getVectorElementType()
421 case v1i32: in getVectorNumElements()
466 case v1i32: return 32; in getSizeInBits()
624 if (NumElements == 1) return MVT::v1i32; in getVectorVT()
DValueTypes.td64 def v1i32 : ValueType<32 , 38>; // 1 x i32 vector value
/external/clang/test/CodeGen/
Dsystemz-abi-vector.c17 typedef __attribute__((vector_size(4))) int v1i32; typedef
82 v1i32 pass_v1i32(v1i32 arg) { return arg; } in pass_v1i32()
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td344 // D form - v1i8, v1i16, v1i32, v1i64
371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
420 // D form - v1i32, v1i64
435 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
442 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
473 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
482 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
497 // D form - v1i8, v1i16, v1i32, v1i64
511 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
[all …]
DAArch64SchedKryoDetails.td148 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
214 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
232 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
262 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
274 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
694 (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;
736 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
772 (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;
1799 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1805 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
DAArch64InstrFormats.td5687 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, []>;
5694 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5699 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm,
5706 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
5916 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
5926 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,
5939 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm,
5954 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5969 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm,
7290 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
[all …]
DAArch64ISelLowering.cpp10163 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 in getPreferredVectorAction()
/external/llvm/test/CodeGen/ARM/
Dv1-constant-fold.ll3 ; PR15611. Check that we don't crash when constant folding v1i32 types.
Dcttz_vector.ll16 declare <1 x i32> @llvm.cttz.v1i32(<1 x i32>, i1)
130 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 false)
312 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 true)
/external/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
11 ; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
Darm64-neon-copy.ll872 define <4 x i32> @testDUP.v1i32(<1 x i32> %a) {
873 ; CHECK-LABEL: testDUP.v1i32:
/external/llvm/lib/IR/
DValueTypes.cpp170 case MVT::v1i32: return "v1i32"; in getEVTString()
248 case MVT::v1i32: return VectorType::get(Type::getInt32Ty(Context), 1); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp98 case MVT::v1i32: return "MVT::v1i32"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td197 def llvm_v1i32_ty : LLVMType<v1i32>; // 1 x i32
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1976 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32, in HexagonTargetLowering()