Searched refs:v32i32 (Results 1 – 12 of 12) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
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| D | HexagonISelLowering.cpp | 203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
419 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || in RetCC_Hexagon()
421 LocVT = MVT::v32i32; in RetCC_Hexagon()
422 ValVT = MVT::v32i32; in RetCC_Hexagon()
439 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
490 } else if (LocVT == MVT::v32i32) { in RetCC_HexagonVector()
545 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
898 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 || in getIndexedAddressParts()
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| D | HexagonRegisterInfo.td | 230 [v128i8, v64i16, v32i32, v16i64], 1024,
234 [v128i8, v64i16, v32i32, v16i64], 1024,
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| D | HexagonInstrInfoV60.td | 800 defm : STrivv_pats <v32i32, v64i32>;
850 defm : vS32b_ai_pats <v16i32, v32i32>;
875 defm : LDrivv_pats <v32i32, v64i32>;
915 defm : vL32b_ai_pats <v16i32, v32i32>;
1589 def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs),
1593 def: Pat<(v64i32 (HexagonVCOMBINE (v32i32 VecDblRegs:$Vs),
1594 (v32i32 VecDblRegs:$Vt))),
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| D | HexagonISelDAGToDAG.cpp | 287 case MVT::v32i32: in SelectIndexedLoad()
575 case MVT::v32i32: in SelectIndexedStore()
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| D | HexagonInstrInfo.cpp | 2632 if (VT == MVT::v32i32 || VT == MVT::v16i64 || in isValidAutoIncImm()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 92 v32i32 = 43, // 32 x i32 enumerator
273 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
347 case v32i32: in getVectorElementType()
387 case v32i32: in getVectorNumElements()
506 case v32i32: in getSizeInBits()
629 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
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| D | ValueTypes.td | 69 def v32i32 : ValueType<1024,43>; // 32 x i32 vector value
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | bitconvert-vector.ll | 3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 175 case MVT::v32i32: return "v32i32"; in getEVTString()
253 case MVT::v32i32: return VectorType::get(Type::getInt32Ty(Context), 32); in getTypeForEVT()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 103 case MVT::v32i32: return "MVT::v32i32"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 202 def llvm_v32i32_ty : LLVMType<v32i32>; // 32 x i32
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