Home
last modified time | relevance | path

Searched refs:v4f16 (Results 1 – 18 of 18) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Dfp16-vector-load-store.ll43 ; Load to one lane of v4f16
63 ; Simple store of v4f16
81 ; Store from one lane of v4f16
102 declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>*)
103 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>*)
104 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 …
105 declare void @llvm.aarch64.neon.st2.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>*)
106 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
107 declare void @llvm.aarch64.neon.st4.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>, <…
115 ; Load 2 x v4f16 with de-interleaving
[all …]
Dfp16-vector-nvcast.ll3 ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
14 ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
36 ; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
Darm64-aapcs.ll139 ; Check that v4f16 can be passed and returned in registers
153 ; Check that v4f16 can be passed and returned on the stack
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h108 v4f16 = 53, // 4 x f16 enumerator
243 SimpleTy == MVT::v4f16 || SimpleTy == MVT::v2f32 || in is64BitVector()
357 case v4f16: in getVectorElementType()
408 case v4f16: in getVectorNumElements()
475 case v4f16: in getSizeInBits()
645 if (NumElements == 4) return MVT::v4f16; in getVectorVT()
DValueTypes.td82 def v4f16 : ValueType<64 , 53>; // 4 x f16 vector value
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2750 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2777 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2804 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2831 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2858 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2885 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2912 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2939 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2966 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
2990 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
[all …]
DAArch64CallingConvention.td31 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
73 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
82 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
96 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
111 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
162 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
172 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
191 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
DAArch64InstrInfo.td1387 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1430 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1574 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1735 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2055 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
2148 def : Pat<(store (v4f16 FPR64:$Rt),
2245 def : Pat<(store (v4f16 FPR64:$Rt),
2357 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2411 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2796 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
[all …]
DAArch64ISelLowering.cpp91 addDRTypeForNEON(MVT::v4f16); in AArch64TargetLowering()
299 setOperationAction(ISD::FADD, MVT::v4f16, Promote); in AArch64TargetLowering()
300 setOperationAction(ISD::FSUB, MVT::v4f16, Promote); in AArch64TargetLowering()
301 setOperationAction(ISD::FMUL, MVT::v4f16, Promote); in AArch64TargetLowering()
302 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); in AArch64TargetLowering()
303 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
304 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
305 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
306 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
307 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
[all …]
DAArch64InstrFormats.td4453 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
4455 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4475 def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
4477 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4496 def v4f16 : BaseSIMDThreeSameVectorTied<0, U, {S,0b10}, {0b00,opc}, V64,
4498 [(set (v4f16 V64:$dst),
4499 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4849 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
4851 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
4882 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
[all …]
DAArch64RegisterInfo.td397 v1i64, v4f16],
/external/llvm/lib/IR/
DValueTypes.cpp187 case MVT::v4f16: return "v4f16"; in getEVTString()
263 case MVT::v4f16: return VectorType::get(Type::getHalfTy(Context), 4); in getTypeForEVT()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td3253 def v4f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3256 [(set DPR:$Vd, (v4i16 (OpNode (v4f16 DPR:$Vm))))]>,
4123 v4f16, v4f16, fadd, 1>,
4184 v4f16, v4f16, fmul, 1>,
4193 def VMULslhd : N3VDSL16<0b01, 0b1001, "vmul", "f16", v4f16, fmul>,
4196 v4f16, fmul>,
4307 v4f16, fmul_su, fadd_mlx>,
4321 v4f16, fmul, fadd>,
4324 v8f16, v4f16, fmul, fadd>,
4537 v4f16, fmul, fsub>,
[all …]
DARMRegisterInfo.td291 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
304 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
309 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp113 case MVT::v4f16: return "MVT::v4f16"; in getEnumName()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp143 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
153 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
205 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
215 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
/external/llvm/include/llvm/IR/
DIntrinsics.td215 def llvm_v4f16_ty : LLVMType<v4f16>; // 4 x half (__fp16)
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in NVPTXTargetLowering()
217 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in NVPTXTargetLowering()