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/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td42 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
47 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
52 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB))]>;
57 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRC))]>;
62 [(set v4f64:$FRT, (IntID v4f64:$FRB))]>;
67 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB))]>;
72 [(set v4f64:$FRT, (IntID v4f64:$FRB))]>;
115 [(set v4f64:$FRT, (fadd v4f64:$FRA, v4f64:$FRB))]>;
126 [(set v4f64:$FRT, (fsub v4f64:$FRA, v4f64:$FRB))]>;
137 [(set v4f64:$FRT, (PPCfre v4f64:$FRB))]>;
[all …]
DPPCISelLowering.cpp675 setOperationAction(ISD::FADD, MVT::v4f64, Legal); in PPCTargetLowering()
676 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in PPCTargetLowering()
677 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); in PPCTargetLowering()
678 setOperationAction(ISD::FREM, MVT::v4f64, Expand); in PPCTargetLowering()
680 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal); in PPCTargetLowering()
681 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
683 setOperationAction(ISD::LOAD , MVT::v4f64, Custom); in PPCTargetLowering()
684 setOperationAction(ISD::STORE , MVT::v4f64, Custom); in PPCTargetLowering()
686 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
687 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
[all …]
/external/llvm/test/CodeGen/X86/
Dvector-intrinsics.ll3 declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
4 declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
5 declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
6 declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32)
10 %t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p)
15 %t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p)
20 %t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
25 %t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
Dvec_floor.ll46 %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
49 declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
108 %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
111 declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
170 %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
173 declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
232 %t = call <4 x double> @llvm.rint.v4f64(<4 x double> %p)
235 declare <4 x double> @llvm.rint.v4f64(<4 x double> %p)
294 %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
297 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
Dfma-phi-213-to-231.ll28 %add = call <4 x double> @llvm.fma.v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %acc.04)
37 declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>)
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dvector-intrinsics.ll3 declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
4 declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
5 declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
6 declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32)
10 %t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p)
15 %t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p)
20 %t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
25 %t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
/external/llvm/test/CodeGen/PowerPC/
Dqpx-rounding-ops.ll20 %call = tail call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone
30 declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone
46 %call = tail call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %x) nounwind readnone
56 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) nounwind readnone
72 %call = tail call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
82 declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
98 %call = tail call <4 x double> @llvm.trunc.v4f64(<4 x double> %x) nounwind readnone
108 declare <4 x double> @llvm.trunc.v4f64(<4 x double>) nounwind readnone
Dvec_rounding.ll19 declare <4 x double> @llvm.floor.v4f64(<4 x double> %p)
22 %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
41 declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
44 %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
63 declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
66 %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
85 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
88 %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
Dqpx-recipest.ll6 declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
11 %x = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
61 %x = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %b)
148 %r = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
Dvec_sqrt.ll13 declare <4 x double> @llvm.sqrt.v4f64(<4 x double> %val)
64 %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x)
Dvec_fmuladd.ll10 declare <4 x double> @llvm.fmuladd.v4f64(<4 x double> %val, <4 x double>, <4 x double>)
49 …%fmuladd = call <4 x double> @llvm.fmuladd.v4f64 (<4 x double> %x, <4 x double> %x, <4 x double> %…
Dctr-minmaxnum.ll18 declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>)
20 declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>)
113 …%0 = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %f, <4 x double> <double 1.0, double 1.0, d…
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h75 v4f64 = 32, // 4 x f64 enumerator
78 LAST_VECTOR_VALUETYPE = v4f64,
147 (SimpleTy >= MVT::v2f32 && SimpleTy <= MVT::v4f64)); in isFloatingPoint()
210 case v4f64: return f64; in getVectorElementType()
231 case v4f64: return 4; in getVectorNumElements()
283 case v4f64: return 256; in getSizeInBits()
369 if (NumElements == 4) return MVT::v4f64; in getVectorVT()
504 return (V == MVT::v8f32 || V == MVT::v4f64 || V == MVT::v32i8 || in is256BitVector()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp443 {ISD::VECTOR_SHUFFLE, MVT::v4f64, 1}, // vblendpd in getShuffleCost()
538 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, in getCastInstrCost()
546 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, in getCastInstrCost()
589 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, in getCastInstrCost()
594 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, in getCastInstrCost()
601 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, in getCastInstrCost()
607 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 }, in getCastInstrCost()
674 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
677 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
680 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, in getCastInstrCost()
[all …]
DX86InstrFMA.td107 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
109 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
112 v2f64, v4f64>, VEX_W;
115 v2f64, v4f64>, VEX_W;
127 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
130 v4f64>, VEX_W;
428 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
430 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
432 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
434 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h117 v4f64 = 62, // 4 x f64 enumerator
257 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
366 case v4f64: in getVectorElementType()
410 case v4f64: return 4; in getVectorNumElements()
495 case v4f64: return 256; in getSizeInBits()
658 if (NumElements == 4) return MVT::v4f64; in getVectorVT()
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.rint.f64.ll38 %0 = call <4 x double> @llvm.rint.v4f64(<4 x double> %in)
46 declare <4 x double> @llvm.rint.v4f64(<4 x double>) #0
Dfnearbyint.ll13 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) #0
52 %0 = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %in)
Dfcopysign.f64.ll6 declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind readnone
37 %result = call <4 x double> @llvm.copysign.v4f64(<4 x double> %mag, <4 x double> %sign)
Dllvm.round.f64.ll50 %result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1
67 declare <4 x double> @llvm.round.v4f64(<4 x double>) #1
Dfma.f64.ll6 declare <4 x double> @llvm.fma.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
44 … %r3 = tail call <4 x double> @llvm.fma.v4f64(<4 x double> %r0, <4 x double> %r1, <4 x double> %r2)
Dfminnum.f64.ll6 declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>) #0
33 %val = call <4 x double> @llvm.minnum.v4f64(<4 x double> %a, <4 x double> %b) #0
Dfmaxnum.f64.ll6 declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>) #0
33 %val = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %a, <4 x double> %b) #0
/external/llvm/test/CodeGen/AArch64/
Dvector-fcopysign.ll147 ;============ v4f64
160 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0)
172 %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b)
176 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenDAGISel.inc134 /*258*/ OPC_CheckChild1Type, MVT::v4f64,
143 …// Src: (st VR256:v4f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
144 // Dst: (VMOVNTPDYmr addr:iPTR:$dst, VR256:v4f64:$src)
148 …// Src: (st VR256:v4f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
149 // Dst: (VMOVNTDQY_64mr addr:iPTR:$dst, VR256:v4f64:$src)
5554 /*12196*/ OPC_CheckChild1Type, MVT::v4f64,
5565 …// Src: (st VR256:v4f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<…
5566 // Dst: (VMOVAPDYmr addr:iPTR:$dst, VR256:v4f64:$src)
5573 …// Src: (st VR256:v4f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> -…
5574 // Dst: (VMOVUPDYmr addr:iPTR:$dst, VR256:v4f64:$src)
[all …]

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