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Searched refs:v4i1 (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td231 [(set v4f64:$FRT, (vselect v4i1:$FRA,
237 [(set v4f32:$FRT, (vselect v4i1:$FRA,
243 [(set v4i1:$FRT, (vselect v4i1:$FRA,
244 v4i1:$FRC, v4i1:$FRB))]>;
271 [(set v4i1:$dst,
272 (select i1:$cond, v4i1:$T, v4i1:$F))]>;
349 [/* (set v4i1:$FRT, v4i1:$FRB) */]>;
405 [(set v4i1:$FRT,
406 (PPCqvaligni v4i1:$FRA, v4i1:$FRB,
424 [(set v4i1:$FRT,
[all …]
DPPCCallingConv.td63 CCIfType<[v4f64, v4f32, v4i1],
119 CCIfType<[v4f64, v4f32, v4i1],
169 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
186 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
DPPCISelLowering.cpp774 setOperationAction(ISD::AND , MVT::v4i1, Legal); in PPCTargetLowering()
775 setOperationAction(ISD::OR , MVT::v4i1, Legal); in PPCTargetLowering()
776 setOperationAction(ISD::XOR , MVT::v4i1, Legal); in PPCTargetLowering()
779 setOperationAction(ISD::SELECT, MVT::v4i1, Expand); in PPCTargetLowering()
780 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal); in PPCTargetLowering()
782 setOperationAction(ISD::LOAD , MVT::v4i1, Custom); in PPCTargetLowering()
783 setOperationAction(ISD::STORE , MVT::v4i1, Custom); in PPCTargetLowering()
785 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom); in PPCTargetLowering()
786 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); in PPCTargetLowering()
787 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
[all …]
DPPCRegisterInfo.td326 def QBRC : RegisterClass<"PPC", [v4i1], 256, (add QFRC)> {
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h60 v4i1 = 14, // 4 x i1 enumerator
318 case v4i1: in getVectorElementType()
403 case v4i1: in getVectorNumElements()
450 case v4i1: return 4; in getSizeInBits()
594 if (NumElements == 4) return MVT::v4i1; in getVectorVT()
DValueTypes.td37 def v4i1 : ValueType<4 , 14>; // 4 x i1 vector value
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td15 def V4I1: PatLeaf<(v4i1 PredRegs:$R)>;
231 def: vcmp_vi1_pat<A2_vcmpheq, seteq, V4I16, v4i1>;
232 def: vcmp_vi1_pat<A2_vcmphgt, setgt, V4I16, v4i1>;
233 def: vcmp_vi1_pat<A2_vcmphgtu, setugt, V4I16, v4i1>;
309 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, v4i1>;
316 def: InvertCmp_pat<A2_vcmphgtu, setult, V4I16, v4i1>;
DHexagonRegisterInfo.td248 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp617 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
618 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
648 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, in getCastInstrCost()
649 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, in getCastInstrCost()
673 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
674 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
686 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, in getCastInstrCost()
687 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, in getCastInstrCost()
DX86CallingConv.td47 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
324 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
597 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
DX86RegisterInfo.td513 def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}
521 def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
DX86InstrAVX512.td2040 def : Pat<(v4i1 (load addr:$src)),
2065 def : Pat<(v4i1 (load addr:$src)),
2152 def : Pat<(v4i1 (scalar_to_vector VK1:$src)),
2245 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2344 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2451 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2468 defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>;
2474 defm : operation_subvector_mask_lowering<VK4, v4i1, VK8, v8i1>;
2475 defm : operation_subvector_mask_lowering<VK4, v4i1, VK16, v16i1>;
2476 defm : operation_subvector_mask_lowering<VK4, v4i1, VK32, v32i1>;
[all …]
/external/llvm/lib/IR/
DValueTypes.cpp146 case MVT::v4i1: return "v4i1"; in getEVTString()
224 case MVT::v4i1: return VectorType::get(Type::getInt1Ty(Context), 4); in getTypeForEVT()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp138 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
139 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
301 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
/external/llvm/test/CodeGen/X86/
Dsse1.ll37 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type)
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-15.ll32 ; Test a v4i1->v4i32 extension.
Dvec-move-16.ll32 ; Test a v4i1->v4i32 extension.
Dvec-move-17.ll32 ; Test a v4i32->v4i1 truncation.
Dvec-and-03.ll38 ; Test a v4i1->v4i32 extension.
Dvec-shift-07.ll38 ; Test a v4i1->v4i32 extension.
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp71 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
72 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
86 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
DSIISelLowering.cpp113 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); in SITargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp74 case MVT::v4i1: return "MVT::v4i1"; in getEnumName()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp449 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
/external/llvm/include/llvm/IR/
DIntrinsics.td170 def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1

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