/external/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost() 124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost() 154 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost() 155 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost() 156 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost() 197 { ISD::SHL, MVT::v8i32, 2 }, in getArithmeticInstrCost() 198 { ISD::SRL, MVT::v8i32, 4 }, in getArithmeticInstrCost() 199 { ISD::SRA, MVT::v8i32, 4 }, in getArithmeticInstrCost() 226 { ISD::SDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost() 230 { ISD::UDIV, MVT::v8i32, 8*20 }, in getArithmeticInstrCost() [all …]
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D | X86InstrSSE.td | 340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))), 341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>; 363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>; 420 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>; 425 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>; 426 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>; 427 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>; 428 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>; 429 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>; 431 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>; [all …]
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D | X86CallingConv.td | 62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 118 CCIfType<[v8f32, v4f64, v8i32, v4i64], 145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 340 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 362 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 403 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>, 445 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 520 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 536 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 555 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], [all …]
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D | X86RegisterInfo.td | 471 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 480 def VR256L : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 482 def VR256H : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 507 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
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/external/llvm/test/CodeGen/AMDGPU/ |
D | llvm.SI.gather4.ll | 86 …%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde… 153 …%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde… 179 …%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef… 205 …%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef… 218 …%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> un… 272 …%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> unde… 298 …%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef… 324 …%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef… 337 …%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> un… 378 …%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef… [all …]
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D | bswap.ll | 7 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone 91 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
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/external/llvm/test/CodeGen/X86/ |
D | pr28515.ll | 10 …%wide.masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* bitcast (i32* getele… 14 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) #0
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D | vector-popcnt-256.ll | 95 %out = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %in) 194 …%out = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> <i32 256, i32 -1, i32 0, i32 255, i32 -65536, i3… 217 declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>)
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D | bswap-vector.ll | 116 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) 201 %r = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v) 339 %bs1 = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v) 340 %bs2 = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %bs1) 466 …%r = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> <i32 0, i32 1, i32 -1, i32 2, i32 -3, i32 4, i32 -…
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | ValueTypes.h | 65 v8i32 = 23, // 8 x i32 enumerator 201 case v8i32: return i32; in getVectorElementType() 223 case v8i32: in getVectorNumElements() 280 case v8i32: in getSizeInBits() 354 if (NumElements == 8) return MVT::v8i32; in getVectorVT() 505 V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64); in is256BitVector()
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D | ValueTypes.td | 46 def v8i32 : ValueType<256, 23>; // 8 x i32 vector value
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 90 v8i32 = 41, // 8 x i32 enumerator 259 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector() 345 case v8i32: in getVectorElementType() 398 case v8i32: in getVectorNumElements() 492 case v8i32: in getSizeInBits() 627 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64TargetTransformInfo.cpp | 193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost() 201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost() 204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost() 447 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 }, in getCmpSelInstrCost()
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/external/llvm/lib/Target/ARM/ |
D | ARMTargetTransformInfo.cpp | 115 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 116 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost() 126 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost() 146 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost() 147 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstructions.td | 2394 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>; 2525 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, 2536 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>; 2542 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm, 2556 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc, 2570 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da, 2584 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc), 2595 (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc, 2659 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>; 2665 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>; [all …]
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/external/llvm/test/Analysis/CostModel/X86/ |
D | ctbits-cost.ll | 16 declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>) 52 %ctpop = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %a) 100 declare <8 x i32> @llvm.ctlz.v8i32(<8 x i32>, i1) 163 %ctlz = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %a, i1 0) 172 %ctlz = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %a, i1 1) 256 declare <8 x i32> @llvm.cttz.v8i32(<8 x i32>, i1) 319 %cttz = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %a, i1 0) 328 %cttz = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> %a, i1 1)
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D | bswap.ll | 15 declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) 58 %bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
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D | bitreverse.ll | 67 declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>) 111 %bitreverse = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)
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D | masked-intrinsic-cost.ll | 221 call void @llvm.masked.scatter.v8i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> %mask) 225 declare void @llvm.masked.scatter.v8i32(<8 x i32> %a1, <8 x i32*> %ptr, i32, <8 x i1> %mask) 286 declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
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/external/swiftshader/third_party/LLVM/lib/VMCore/ |
D | ValueTypes.cpp | 131 case MVT::v8i32: return "v8i32"; in getEVTString() 178 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8); in getTypeForEVT()
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/external/llvm/test/Transforms/InstSimplify/ |
D | call.ll | 212 …%masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* bitcast (i32* getelementp… 219 …%masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %V, i32 4, <8 x i1> undef… 225 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86CallingConv.td | 46 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 162 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 178 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 277 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 285 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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D | X86InstrFragmentsSIMD.td | 217 def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; 263 (v8i32 (alignedload256 node:$ptr))>; 294 def memopv8i32 : PatFrag<(ops node:$ptr), (v8i32 (memop node:$ptr))>; 340 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
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/external/llvm/test/CodeGen/ARM/ |
D | isel-v8i32-crash.ll | 9 ; when we have a vector length of 8, due to use of v8i32 types.
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 173 case MVT::v8i32: return "v8i32"; in getEVTString() 251 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8); in getTypeForEVT()
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