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Searched refs:v_cndmask_b32_e32 (Results 1 – 16 of 16) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dselect-vectors.ll9 ; SI: v_cndmask_b32_e32
10 ; SI: v_cndmask_b32_e32
11 ; SI: v_cndmask_b32_e32
12 ; SI: v_cndmask_b32_e32
21 ; SI: v_cndmask_b32_e32
22 ; SI: v_cndmask_b32_e32
23 ; SI: v_cndmask_b32_e32
24 ; SI: v_cndmask_b32_e32
36 ; SI: v_cndmask_b32_e32
37 ; SI: v_cndmask_b32_e32
[all …]
Daddrspacecast.ll15 ; HSA-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]]
16 ; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
38 ; HSA-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]]
39 ; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
84 ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
101 ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
Dcndmask-no-def-vcc.ll9 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
36 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
Dselect64.ll54 ; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
55 ; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 63, {{v[0-9]+}}
Duint_to_fp.f64.ll73 ; We can't fold the SGPRs into v_cndmask_b32_e32, because it already
78 ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
Dvselect.ll11 ; SI: v_cndmask_b32_e32
29 ;SI: v_cndmask_b32_e32
Dselect-i1.ll21 ; SI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
Dsint_to_fp.f64.ll18 ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
Dllvm.round.ll13 ; SI: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[VX]]
Dsminmax.ll209 ; GCN-DAG: v_cndmask_b32_e32
210 ; GCN-DAG: v_cndmask_b32_e32
Dxor.ll46 ; SI: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
Dctlz_zero_undef.ll101 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
Dctlz.ll121 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
/external/llvm/test/MC/AMDGPU/
Dvop2-err.s26 v_cndmask_b32_e32 v1, v2, v3, s[0:1] label
Dvop2.s113 v_cndmask_b32_e32 v1, v2, v3, vcc label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt3 # VI: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]