Searched refs:v_cndmask_b32_e32 (Results 1 – 16 of 16) sorted by relevance
/external/llvm/test/CodeGen/AMDGPU/ |
D | select-vectors.ll | 9 ; SI: v_cndmask_b32_e32 10 ; SI: v_cndmask_b32_e32 11 ; SI: v_cndmask_b32_e32 12 ; SI: v_cndmask_b32_e32 21 ; SI: v_cndmask_b32_e32 22 ; SI: v_cndmask_b32_e32 23 ; SI: v_cndmask_b32_e32 24 ; SI: v_cndmask_b32_e32 36 ; SI: v_cndmask_b32_e32 37 ; SI: v_cndmask_b32_e32 [all …]
|
D | addrspacecast.ll | 15 ; HSA-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]] 16 ; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 38 ; HSA-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]] 39 ; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] 84 ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] 101 ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
|
D | cndmask-no-def-vcc.ll | 9 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc 36 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
|
D | select64.ll | 54 ; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} 55 ; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 63, {{v[0-9]+}}
|
D | uint_to_fp.f64.ll | 73 ; We can't fold the SGPRs into v_cndmask_b32_e32, because it already 78 ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
|
D | vselect.ll | 11 ; SI: v_cndmask_b32_e32 29 ;SI: v_cndmask_b32_e32
|
D | select-i1.ll | 21 ; SI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]]
|
D | sint_to_fp.f64.ll | 18 ; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
|
D | llvm.round.ll | 13 ; SI: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[VX]]
|
D | sminmax.ll | 209 ; GCN-DAG: v_cndmask_b32_e32 210 ; GCN-DAG: v_cndmask_b32_e32
|
D | xor.ll | 46 ; SI: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
|
D | ctlz_zero_undef.ll | 101 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
|
D | ctlz.ll | 121 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
|
/external/llvm/test/MC/AMDGPU/ |
D | vop2-err.s | 26 v_cndmask_b32_e32 v1, v2, v3, s[0:1] label
|
D | vop2.s | 113 v_cndmask_b32_e32 v1, v2, v3, vcc label
|
/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop2_vi.txt | 3 # VI: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
|