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Searched refs:v_readlane_b32 (Results 1 – 6 of 6) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dbasic-branch.ll13 ; GCNNOOPT: v_readlane_b32
14 ; GCNNOOPT: v_readlane_b32
Dm0-spill.ll7 ; CHECK-NOT: v_readlane_b32 m0
Dsi-spill-cf.ll8 ; SI-NOT: v_readlane_b32 [[SAVED]]
/external/llvm/test/MC/AMDGPU/
Dvop2.s117 v_readlane_b32 s1, v2, s3 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt6 # VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1594 "v_readlane_b32",
1597 "v_readlane_b32 $vdst, $src0, $src1"
2080 // It's unclear whether you can use M0 as the output of v_readlane_b32