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/external/libcxx/test/libcxx/atomics/
Ddiagnose_invalid_memory_order.fail.cpp23 int val2 = 2; ((void)val2); in main() local
74 …x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_release); // expe… in main()
75 …x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acq_rel); // expe… in main()
76 …vx.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_release); // exp… in main()
77 …vx.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acq_rel); // exp… in main()
79 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_relaxed); in main()
80 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_consume); in main()
81 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_acquire); in main()
82 x.compare_exchange_weak(val1, val2, std::memory_order_seq_cst, std::memory_order_seq_cst); in main()
85 x.compare_exchange_weak(val1, val2, std::memory_order_release); in main()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dicmp32.ll16 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
17 ; $3 = %arg1, $4 = %val1, $5 = %val2
29 define i32 @icmp_eq_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
32 %B = select i1 %A, i32 %val1, i32 %val2
36 define i1 @icmp_eq_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
42 define i32 @icmp_eq_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
45 %B = select i1 %A, i32 %val1, i32 %val2
49 define i32 @icmp_eq_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
52 %B = select i1 %A, i32 %val1, i32 %val2
56 define i32 @icmp_eq_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
[all …]
Dicmp16.ll16 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
17 ; $3 = %arg1, $4 = %val1, $5 = %val2
29 define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
32 %B = select i1 %A, i16 %val1, i16 %val2
36 define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
42 define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
45 %B = select i1 %A, i16 %val1, i16 %val2
49 define i16 @icmp_eq_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
52 %B = select i1 %A, i16 %val1, i16 %val2
56 define i16 @icmp_eq_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
[all …]
Dicmp8.ll15 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
16 ; $3 = %arg1, $4 = %val1, $5 = %val2
28 define i8 @icmp_eq_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
31 %B = select i1 %A, i8 %val1, i8 %val2
35 define i1 @icmp_eq_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
41 define i8 @icmp_eq_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
44 %B = select i1 %A, i8 %val1, i8 %val2
48 define i8 @icmp_eq_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
51 %B = select i1 %A, i8 %val1, i8 %val2
55 define i8 @icmp_eq_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
[all …]
Dicmp64.ll14 ; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
15 ; $3 = %arg1, $4 = %val1, $5 = %val2
18 define i64 @icmp_eq_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
21 %B = select i1 %A, i64 %val1, i64 %val2
25 define i1 @icmp_eq_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
31 define i64 @icmp_ne_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
34 %B = select i1 %A, i64 %val1, i64 %val2
38 define i1 @icmp_ne_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
44 define i64 @icmp_ugt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
47 %B = select i1 %A, i64 %val1, i64 %val2
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 ret <16 x i8> %val2
14 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
18 ret <8 x i16> %val2
22 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
26 ret <4 x i32> %val2
30 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
34 ret <2 x i64> %val2
38 define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
42 ret <4 x float> %val2
[all …]
Dvec-max-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val1, %val2
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val1, %val2
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val1, %val2
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-min-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val2, %val1
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val2, %val1
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val2, %val1
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-max-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val1, %val2
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val1, %val2
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val1, %val2
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-min-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val2, %val1
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val2, %val1
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val2, %val1
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-max-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val1, %val2
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val1, %val2
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val1, %val2
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-min-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val2, %val1
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val2, %val1
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val2, %val1
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val2, %val1
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val2, %val1
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val2, %val1
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-max-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val1, %val2
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val1, %val2
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val1, %val2
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-cmp-03.ll6 define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp eq <4 x i32> %val1, %val2
16 define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
21 %cmp = icmp ne <4 x i32> %val1, %val2
27 define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
31 %cmp = icmp sgt <4 x i32> %val1, %val2
37 define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
42 %cmp = icmp sge <4 x i32> %val1, %val2
48 define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
53 %cmp = icmp sle <4 x i32> %val1, %val2
[all …]
Dvec-cmp-04.ll6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp eq <2 x i64> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
21 %cmp = icmp ne <2 x i64> %val1, %val2
27 define <2 x i64> @f3(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
31 %cmp = icmp sgt <2 x i64> %val1, %val2
37 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
42 %cmp = icmp sge <2 x i64> %val1, %val2
48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
53 %cmp = icmp sle <2 x i64> %val1, %val2
[all …]
Dvec-cmp-01.ll6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp eq <16 x i8> %val1, %val2
16 define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
21 %cmp = icmp ne <16 x i8> %val1, %val2
27 define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
31 %cmp = icmp sgt <16 x i8> %val1, %val2
37 define <16 x i8> @f4(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
42 %cmp = icmp sge <16 x i8> %val1, %val2
48 define <16 x i8> @f5(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
53 %cmp = icmp sle <16 x i8> %val1, %val2
[all …]
Dvec-cmp-02.ll6 define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp eq <8 x i16> %val1, %val2
16 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
21 %cmp = icmp ne <8 x i16> %val1, %val2
27 define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
31 %cmp = icmp sgt <8 x i16> %val1, %val2
37 define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
42 %cmp = icmp sge <8 x i16> %val1, %val2
48 define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
53 %cmp = icmp sle <8 x i16> %val1, %val2
[all …]
Dvec-cmp-06.ll6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
10 %cmp = fcmp oeq <2 x double> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
22 %cmp = fcmp one <2 x double> %val1, %val2
28 define <2 x i64> @f3(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
32 %cmp = fcmp ogt <2 x double> %val1, %val2
38 define <2 x i64> @f4(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
42 %cmp = fcmp oge <2 x double> %val1, %val2
48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
52 %cmp = fcmp ole <2 x double> %val1, %val2
[all …]
Dvec-perm-08.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
19 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
23 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
32 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
36 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
45 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
49 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
71 define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) {
75 %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
[all …]
/external/valgrind/none/tests/s390x/
Dcgrj.c31 register int64_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register int64_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register int64_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register int64_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register int64_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dclgrj.c31 register uint64_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register uint64_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register uint64_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register uint64_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register uint64_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dcrj.c31 register int32_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register int32_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register int32_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register int32_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register int32_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dclrj.c31 register uint32_t val2 asm("r8") = value2; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
47 register uint32_t val2 asm("r8") = value2; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
63 register uint32_t val2 asm("r8") = value2; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
79 register uint32_t val2 asm("r8") = value2; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
95 register uint32_t val2 asm("r8") = value2; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
/external/libbrillo/brillo/
Dany_unittest.cc19 Any val2 = val; in TEST() local
21 EXPECT_TRUE(val2.IsEmpty()); in TEST()
34 Any val2(3.1415926); in TEST() local
35 EXPECT_FALSE(val2.IsEmpty()); in TEST()
36 EXPECT_TRUE(val2.IsTypeCompatible<double>()); in TEST()
37 EXPECT_FALSE(val2.IsTypeCompatible<int>()); in TEST()
38 EXPECT_DOUBLE_EQ(3.1415926, val2.Get<double>()); in TEST()
66 Any val2; in TEST() local
67 EXPECT_TRUE(val2.IsEmpty()); in TEST()
68 val2 = val; in TEST()
[all …]

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