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Searched refs:vcmp (Results 1 – 25 of 42) sorted by relevance

12

/external/llvm/test/MC/Hexagon/
Dv60-vcmp.s5 #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) }
6 q2|=vcmp.eq(v17.b,v1.b)
8 #CHECK: 1c84fb2a { q2 &= vcmp.gt(v27.uw{{ *}},{{ *}}v4.uw) }
9 q2&=vcmp.gt(v27.uw,v4.uw)
11 #CHECK: 1c8cf826 { q2 &= vcmp.gt(v24.uh{{ *}},{{ *}}v12.uh) }
12 q2&=vcmp.gt(v24.uh,v12.uh)
14 #CHECK: 1c80e720 { q0 &= vcmp.gt(v7.ub{{ *}},{{ *}}v0.ub) }
15 q0&=vcmp.gt(v7.ub,v0.ub)
17 #CHECK: 1c9aed1a { q2 &= vcmp.gt(v13.w{{ *}},{{ *}}v26.w) }
18 q2&=vcmp.gt(v13.w,v26.w)
[all …]
Dv60-misc.s26 # CHECK: 1f90cf00 { q0 = vcmp.eq(v15.b,v16.b) }
27 q0 = vcmp.eq(v15.ub, v16.ub)
29 # CHECK: 1c92f101 { q1 &= vcmp.eq(v17.b,v18.b) }
30 q1 &= vcmp.eq(v17.ub, v18.ub)
32 # CHECK: 1c94f342 { q2 |= vcmp.eq(v19.b,v20.b) }
33 q2 |= vcmp.eq(v19.ub, v20.ub)
35 # CHECK: 1c96f583 { q3 ^= vcmp.eq(v21.b,v22.b) }
36 q3 ^= vcmp.eq(v21.ub, v22.ub)
38 # CHECK: 1f81c004 { q0 = vcmp.eq(v0.h,v1.h) }
39 q0 = vcmp.eq(v0.uh, v1.uh)
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td512 // maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
513 def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
517 // maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
518 def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
522 // maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
523 def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
527 // maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
528 def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
532 // maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
533 def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
[all …]
DHexagonInstrInfoV60.td1477 T_HVX_vcmp <"$dst &= vcmp.eq($src1.b,$src2.b)">, V6_veqb_and_enc;
1479 T_HVX_vcmp <"$dst &= vcmp.eq($src1.h,$src2.h)">, V6_veqh_and_enc;
1481 T_HVX_vcmp <"$dst &= vcmp.eq($src1.w,$src2.w)">, V6_veqw_and_enc;
1483 T_HVX_vcmp <"$dst &= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_and_enc;
1485 T_HVX_vcmp <"$dst &= vcmp.gt($src1.h,$src2.h)">, V6_vgth_and_enc;
1487 T_HVX_vcmp <"$dst &= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_and_enc;
1489 T_HVX_vcmp <"$dst &= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_and_enc;
1491 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_and_enc;
1493 T_HVX_vcmp <"$dst &= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_and_enc;
1495 T_HVX_vcmp <"$dst |= vcmp.eq($src1.b,$src2.b)">, V6_veqb_or_enc;
[all …]
/external/llvm/test/CodeGen/ARM/
Dvminmaxnm.ll7 ; CHECK-NOT: vcmp
16 ; CHECK-NOT: vcmp
25 ; CHECK-NOT: vcmp
34 ; CHECK-NOT: vcmp
43 ; CHECK-NOT: vcmp
52 ; CHECK-NOT: vcmp
61 ; CHECK-NOT: vcmp
70 ; CHECK-NOT: vcmp
79 ; CHECK-NOT: vcmp
88 ; CHECK-NOT: vcmp
[all …]
Dfpcmp-f64-neon-opt.ll8 ; CHECK: vcmp
/external/llvm/test/MC/ARM/
Dfullfp16.s40 vcmp.f16 s0, s1
41 @ ARM: vcmp.f16 s0, s1 @ encoding: [0x60,0x09,0xb4,0xee]
42 @ THUMB: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
44 vcmp.f16 s2, #0
45 @ ARM: vcmp.f16 s2, #0 @ encoding: [0x40,0x19,0xb5,0xee]
46 @ THUMB: vcmp.f16 s2, #0 @ encoding: [0xb5,0xee,0x40,0x19]
Dsingle-precision-fp.s57 vcmp.f64 d2, d3
60 vcmp.f64 d6, #0
64 @ CHECK-ERRORS-NEXT: vcmp.f64 d2, d3
70 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
Dfullfp16-neg.s31 vcmp.f16 s0, s1
34 vcmp.f16 s2, #0
/external/compiler-rt/lib/builtins/arm/
Deqsf2vfp.S24 vcmp.f32 s14, s15
Dgesf2vfp.S24 vcmp.f32 s14, s15
Dltsf2vfp.S24 vcmp.f32 s14, s15
Dunordsf2vfp.S24 vcmp.f32 s14, s15
Dgtsf2vfp.S24 vcmp.f32 s14, s15
Dlesf2vfp.S24 vcmp.f32 s14, s15
Dnesf2vfp.S24 vcmp.f32 s14, s15
Dnedf2vfp.S24 vcmp.f64 d6, d7
Deqdf2vfp.S24 vcmp.f64 d6, d7
Dgtdf2vfp.S24 vcmp.f64 d6, d7
Dunorddf2vfp.S24 vcmp.f64 d6, d7
Dgedf2vfp.S24 vcmp.f64 d6, d7
Dltdf2vfp.S24 vcmp.f64 d6, d7
Dledf2vfp.S24 vcmp.f64 d6, d7
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-thumb.txt30 # CHECK: vcmp.f16 s0, s1
33 # CHECK: vcmp.f16 s2, #0
Dfullfp16-arm.txt30 # CHECK: vcmp.f16 s0, s1
33 # CHECK: vcmp.f16 s2, #0

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