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Searched refs:vcnt (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/test/CodeGen/PowerPC/
Dvec_popcnt.ll13 %vcnt = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp)
14 ret <16 x i8> %vcnt
22 %vcnt = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp)
23 ret <8 x i16> %vcnt
31 %vcnt = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp)
32 ret <4 x i32> %vcnt
39 %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x)
40 ret <2 x i64> %vcnt
48 %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp)
49 ret <2 x i64> %vcnt
[all …]
Dvec_clz.ll11 %vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x)
12 ret <16 x i8> %vcnt
19 %vcnt = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x)
20 ret <8 x i16> %vcnt
27 %vcnt = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x)
28 ret <4 x i32> %vcnt
35 %vcnt = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x)
36 ret <2 x i64> %vcnt
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-bitcount-encoding.s3 @ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3]
4 vcnt.8 d16, d16
5 @ CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xf3]
6 vcnt.8 q8, q8
Dneont2-bitcount-encoding.s5 vcnt.8 d16, d16
6 vcnt.8 q8, q8
8 @ CHECK: vcnt.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x05]
9 @ CHECK: vcnt.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x05]
/external/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s3 @ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3]
4 vcnt.8 d16, d16
5 @ CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xf3]
6 vcnt.8 q8, q8
Dneont2-bitcount-encoding.s5 vcnt.8 d16, d16
6 vcnt.8 q8, q8
8 @ CHECK: vcnt.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x05]
9 @ CHECK: vcnt.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x05]
/external/llvm/test/Bitcode/
Darm32_neon_vcnt_upgrade.ll3 ; Tests vclz and vcnt
16 %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
22 declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
/external/libvpx/libvpx/vp8/encoder/
Drdopt.c1352 int vcnt = 0; in vp8_mv_pred() local
1373 near_mvs[vcnt].as_int = above->mbmi.mv.as_int; in vp8_mv_pred()
1375 &near_mvs[vcnt], ref_frame_sign_bias); in vp8_mv_pred()
1376 near_ref[vcnt] = above->mbmi.ref_frame; in vp8_mv_pred()
1378 vcnt++; in vp8_mv_pred()
1380 near_mvs[vcnt].as_int = left->mbmi.mv.as_int; in vp8_mv_pred()
1382 &near_mvs[vcnt], ref_frame_sign_bias); in vp8_mv_pred()
1383 near_ref[vcnt] = left->mbmi.ref_frame; in vp8_mv_pred()
1385 vcnt++; in vp8_mv_pred()
1387 near_mvs[vcnt].as_int = aboveleft->mbmi.mv.as_int; in vp8_mv_pred()
[all …]
/external/ltp/testcases/kernel/io/direct_io/
Ddiotest_routines.c65 void vfillbuf(struct iovec *iv, int vcnt, char value) in vfillbuf() argument
69 for (i = 0; i < vcnt; iv++, i++) { in vfillbuf()
93 int vbufcmp(struct iovec *iv1, struct iovec *iv2, int vcnt) in vbufcmp() argument
97 for (i = 0; i < vcnt; iv1++, iv2++, i++) { in vbufcmp()
Ddiotest_routines.h3 extern void vfillbuf(struct iovec *iv, int vcnt, char value);
6 extern int vbufcmp(struct iovec *iv1, struct iovec *iv2, int vcnt);
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvcnt.ll5 ;CHECK: vcnt.8
7 %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
13 ;CHECK: vcnt.8
15 %tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1)
19 declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
20 declare <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8>) nounwind readnone
/external/llvm/test/CodeGen/ARM/
Dcttz_vector.ll56 ; CHECK: vcnt.8 [[D1]], [[D1]]
71 ; CHECK: vcnt.8 [[Q1]], [[Q1]]
102 ; CHECK: vcnt.8 [[D1]], [[D1]]
118 ; CHECK: vcnt.8 [[Q1]], [[Q1]]
142 ; CHECK: vcnt.8 [[D1]], [[D1]]
159 ; CHECK: vcnt.8 [[Q1]], [[Q1]]
177 ; CHECK: vcnt.8 [[D1]], [[D1]]
196 ; CHECK: vcnt.8 [[Q1]], [[Q1]]
240 ; CHECK: vcnt.8 [[D1]], [[D1]]
255 ; CHECK: vcnt.8 [[Q1]], [[Q1]]
[all …]
Dpopcnt.ll2 ; Implement ctpop with vcnt
6 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
14 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
22 ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
34 ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
46 ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
61 ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
6 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
14 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
/external/arm-neon-tests/
Dref_vcnt.c34 #define INSN_NAME vcnt
DAndroid.mk38 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
DMakefile.gcc59 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
DMakefile53 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
/external/libedit/src/
Dterminal.c1272 ssize_t vcnt = ct_visual_char(visbuf, VISUAL_WIDTH_MAX, c); in terminal_writec() local
1273 if (vcnt < 0) in terminal_writec()
1274 vcnt = 0; in terminal_writec()
1275 visbuf[vcnt] = '\0'; in terminal_writec()
1276 terminal_overwrite(el, visbuf, (size_t)vcnt); in terminal_writec()
/external/vixl/src/aarch32/
Dassembler-aarch32.h4136 void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm);
4137 void vcnt(DataType dt, DRegister rd, DRegister rm) { vcnt(al, dt, rd, rm); } in vcnt() function
4139 void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm);
4140 void vcnt(DataType dt, QRegister rd, QRegister rm) { vcnt(al, dt, rd, rm); } in vcnt() function
Ddisasm-aarch32.h1547 void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm);
1549 void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm);
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt249 # CHECK: vcnt.8 d16, d16
251 # CHECK: vcnt.8 q8, q8
Dneon.txt253 # CHECK: vcnt.8 d16, d16
255 # CHECK: vcnt.8 q8, q8
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt249 # CHECK: vcnt.8 d16, d16
251 # CHECK: vcnt.8 q8, q8
Dneon.txt253 # CHECK: vcnt.8 d16, d16
255 # CHECK: vcnt.8 q8, q8

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