| /external/llvm/test/CodeGen/ARM/ |
| D | inlineasm-X-constraint.ll | 4 ; add a dependency between an assembly instruction (vmsr in this case) and
10 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
15 ; CHECK: vmsr fpscr
22 …call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwi…
29 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
34 ; CHECK: vmsr fpscr
40 call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind
48 ; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value));
58 ; asm volatile ("vmsr fpscr,%1" : "=X" ((vector_res_int8x8)) : "r" (fpscr));
63 ; CHECK: vmsr fpscr
[all …]
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| D | special-reg.ll | 64 ; ARM: vmsr fpscr, r0
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| /external/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 165 @ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
166 vmsr fpscr, r0
167 @ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee]
168 vmsr fpexc, r0
169 @ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
170 vmsr fpsid, r0
171 @ CHECK: vmsr fpinst, r3 @ encoding: [0x10,0x3a,0xe9,0xee]
172 vmsr fpinst, r3
173 @ CHECK: vmsr fpinst2, r4 @ encoding: [0x10,0x4a,0xea,0xee]
174 vmsr fpinst2, r4
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | simple-fp-encoding.s | 137 @ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
138 vmsr fpscr, r0
139 @ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee]
140 vmsr fpexc, r0
141 @ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
142 vmsr fpsid, r0
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 131 # CHECK: vmsr fpscr, r0
133 # CHECK: vmsr fpexc, r0
135 # CHECK: vmsr fpsid, r0
137 # CHECK: vmsr fpinst, r3
139 # CHECK: vmsr fpinst2, r4
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 127 # CHECK: vmsr fpscr, r0
129 # CHECK: vmsr fpexc, r0
131 # CHECK: vmsr fpsid, r0
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | inlineasm-X-constraint.ll | 4 ; add a dependency between an assembly instruction (vmsr in this case) and
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 2124 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
2127 "vmsr", "\tfpexc, $src", []>;
2130 "vmsr", "\tfpsid, $src", []>;
2133 "vmsr", "\tfpinst, $src", []>;
2135 "vmsr", "\tfpinst2, $src", []>;
2244 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 1108 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1111 "vmsr", "\tfpexc, $src", []>;
1114 "vmsr", "\tfpsid, $src", []>;
|
| /external/v8/src/arm/ |
| D | assembler-arm.h | 1203 void vmsr(const Register dst, const Condition cond = al);
|
| D | assembler-arm.cc | 3707 void Assembler::vmsr(Register dst, Condition cond) { in vmsr() function in v8::internal::Assembler
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 4893 void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt);
4894 void vmsr(SpecialFPRegister spec_reg, Register rt) { vmsr(al, spec_reg, rt); } in vmsr() function
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| D | disasm-aarch32.h | 1914 void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt);
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| D | assembler-aarch32.cc | 19976 void Assembler::vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) { in vmsr() function in vixl::aarch32::Assembler
19992 Delegate(kVmsr, &Assembler::vmsr, cond, spec_reg, rt); in vmsr()
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| D | disasm-aarch32.cc | 5390 void Disassembler::vmsr(Condition cond, in vmsr() function in vixl::aarch32::Disassembler
25050 vmsr(CurrentCond(), in DecodeT32()
67508 vmsr(condition, in DecodeA32()
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| D | macro-assembler-aarch32.h | 8026 vmsr(cond, spec_reg, rt); in Vmsr()
|