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Searched refs:vqdmull (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/MC/ARM/
Dneont2-mul-encoding.s71 vqdmull.s16 q8, d16, d17
72 vqdmull.s32 q8, d16, d17
73 vqdmull.s16 q1, d7, d1[1]
75 @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d]
76 @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d]
77 @ CHECK: vqdmull.s16 q1, d7, d1[1] @ encoding: [0x97,0xef,0x49,0x2b]
Dneon-mul-encoding.s99 vqdmull.s16 q8, d16, d17
100 vqdmull.s32 q8, d16, d17
102 @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2]
103 @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2]
Darm_instructions.s18 @ CHECK: vqdmull.s32 q8, d17, d16
20 vqdmull.s32 q8, d17, d16
/external/llvm/test/CodeGen/ARM/
Dvqdmul.ll163 ;CHECK: vqdmull.s16
166 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
172 ;CHECK: vqdmull.s32
175 %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
182 ; CHECK: vqdmull.s16 q0, d0, d1[1]
184 …%1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <…
191 ; CHECK: vqdmull.s32 q0, d0, d1[1]
193 …%1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <…
197 declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
198 declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-mul-encoding.s55 @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x0d]
56 vqdmull.s16 q8, d16, d17
57 @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x0d]
58 vqdmull.s32 q8, d16, d17
Darm_instructions.s11 @ CHECK: vqdmull.s32 q8, d17, d16
13 vqdmull.s32 q8, d17, d16
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvqdmul.ll163 ;CHECK: vqdmull.s16
166 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
172 ;CHECK: vqdmull.s32
175 %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
182 ; CHECK: vqdmull.s16 q0, d0, d1[1]
184 …%1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <…
191 ; CHECK: vqdmull.s32 q0, d0, d1[1]
193 …%1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <…
197 declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
198 declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
/external/arm-neon-tests/
DAndroid.mk25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
Dref_vqdmull.c34 #define INSN vqdmull
Dref_vqdmull_n.c34 #define INSN vqdmull
Dref_vqdmull_lane.c34 #define INSN vqdmull
DMakefile.gcc46 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
DMakefile40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
/external/clang/include/clang/Basic/
Darm_neon.td366 def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (splat $p1, $p2))>;
367 def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0),
440 def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0),
477 def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">;
536 def VQDMULL : SInst<"vqdmull", "wdd", "si">;
1585 def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">;
/external/vixl/src/aarch32/
Dassembler-aarch32.h5214 void vqdmull(
5216 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vqdmull() function
5217 vqdmull(al, dt, rd, rn, rm); in vqdmull()
5220 void vqdmull(Condition cond,
5225 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { in vqdmull() function
5226 vqdmull(al, dt, rd, rn, rm); in vqdmull()
Ddisasm-aarch32.h2074 void vqdmull(
2077 void vqdmull(Condition cond,
Dassembler-aarch32.cc21645 void Assembler::vqdmull( in vqdmull() function in vixl::aarch32::Assembler
21670 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm); in vqdmull()
21673 void Assembler::vqdmull( in vqdmull() function in vixl::aarch32::Assembler
21706 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm); in vqdmull()
Ddisasm-aarch32.cc5843 void Disassembler::vqdmull( in vqdmull() function in vixl::aarch32::Disassembler
5850 void Disassembler::vqdmull( in vqdmull() function in vixl::aarch32::Disassembler
29686 vqdmull(CurrentCond(), in DecodeT32()
29757 vqdmull(CurrentCond(), in DecodeT32()
43782 vqdmull(al, in DecodeA32()
43849 vqdmull(al, in DecodeA32()
Dmacro-assembler-aarch32.h8749 vqdmull(cond, dt, rd, rn, rm); in Vqdmull()
8767 vqdmull(cond, dt, rd, rn, rm); in Vqdmull()
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt705 # CHECK: vqdmull.s16 q8, d16, d17
707 # CHECK: vqdmull.s32 q8, d16, d17
Dneon.txt809 # CHECK: vqdmull.s16 q8, d16, d17
811 # CHECK: vqdmull.s32 q8, d16, d17
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt705 # CHECK: vqdmull.s16 q8, d16, d17
707 # CHECK: vqdmull.s32 q8, d16, d17
Dneon.txt809 # CHECK: vqdmull.s16 q8, d16, d17
811 # CHECK: vqdmull.s32 q8, d16, d17
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td3501 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3503 "vqdmull", "s", int_arm_neon_vqdmull>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4291 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4293 "vqdmull", "s", int_arm_neon_vqdmull>;