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Searched refs:vqneg (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/ARM/
Dneon-neg-encoding.s19 @ CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xf3]
20 vqneg.s8 d16, d16
21 @ CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xf3]
22 vqneg.s16 d16, d16
23 @ CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3]
24 vqneg.s32 d16, d16
25 @ CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xf3]
26 vqneg.s8 q8, q8
27 @ CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xf3]
28 vqneg.s16 q8, q8
[all …]
Dneont2-neg-encoding.s21 @ CHECK: vqneg.s8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x07]
22 vqneg.s8 d16, d16
23 @ CHECK: vqneg.s16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x07]
24 vqneg.s16 d16, d16
25 @ CHECK: vqneg.s32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x07]
26 vqneg.s32 d16, d16
27 @ CHECK: vqneg.s8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x07]
28 vqneg.s8 q8, q8
29 @ CHECK: vqneg.s16 q8, q8 @ encoding: [0xf4,0xff,0xe0,0x07]
30 vqneg.s16 q8, q8
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-neg-encoding.s21 @ CHECK: vqneg.s8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x07]
22 vqneg.s8 d16, d16
23 @ CHECK: vqneg.s16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x07]
24 vqneg.s16 d16, d16
25 @ CHECK: vqneg.s32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x07]
26 vqneg.s32 d16, d16
27 @ CHECK: vqneg.s8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x07]
28 vqneg.s8 q8, q8
29 @ CHECK: vqneg.s16 q8, q8 @ encoding: [0xf4,0xff,0xe0,0x07]
30 vqneg.s16 q8, q8
[all …]
Dneon-neg-encoding.s19 @ CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xf3]
20 vqneg.s8 d16, d16
21 @ CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xf3]
22 vqneg.s16 d16, d16
23 @ CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3]
24 vqneg.s32 d16, d16
25 @ CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xf3]
26 vqneg.s8 q8, q8
27 @ CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xf3]
28 vqneg.s16 q8, q8
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvneg.ll69 ;CHECK: vqneg.s8
71 %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
77 ;CHECK: vqneg.s16
79 %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
85 ;CHECK: vqneg.s32
87 %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
93 ;CHECK: vqneg.s8
95 %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
101 ;CHECK: vqneg.s16
103 %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
[all …]
/external/llvm/test/CodeGen/ARM/
Dvneg.ll69 ;CHECK: vqneg.s8
71 %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
77 ;CHECK: vqneg.s16
79 %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
85 ;CHECK: vqneg.s32
87 %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
93 ;CHECK: vqneg.s8
95 %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
101 ;CHECK: vqneg.s16
103 %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-arith-saturating.ll108 %vqneg.i = tail call i32 @llvm.aarch64.neon.sqneg.i32(i32 %vecext) nounwind
109 ret i32 %vqneg.i
117 %vqneg.i = tail call i64 @llvm.aarch64.neon.sqneg.i64(i64 %vecext) nounwind
118 ret i64 %vqneg.i
/external/arm-neon-tests/
Dref_vqneg.c26 #define INSN_NAME vqneg
DAndroid.mk28 vcombine vmax vmin vneg vqneg vmlal vmlal_lane vmlsl \
DMakefile.gcc49 vcombine vmax vmin vneg vqneg vmlal vmlal_lane vmlsl \
DMakefile43 vcombine vmax vmin vneg vqneg vmlal vmlal_lane vmlsl \
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt725 # CHECK: vqneg.s8 d16, d16
727 # CHECK: vqneg.s16 d16, d16
729 # CHECK: vqneg.s32 d16, d16
731 # CHECK: vqneg.s8 q8, q8
733 # CHECK: vqneg.s16 q8, q8
735 # CHECK: vqneg.s32 q8, q8
Dneon.txt831 # CHECK: vqneg.s8 d16, d16
833 # CHECK: vqneg.s16 d16, d16
835 # CHECK: vqneg.s32 d16, d16
837 # CHECK: vqneg.s8 q8, q8
839 # CHECK: vqneg.s16 q8, q8
841 # CHECK: vqneg.s32 q8, q8
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt725 # CHECK: vqneg.s8 d16, d16
727 # CHECK: vqneg.s16 d16, d16
729 # CHECK: vqneg.s32 d16, d16
731 # CHECK: vqneg.s8 q8, q8
733 # CHECK: vqneg.s16 q8, q8
735 # CHECK: vqneg.s32 q8, q8
Dneon.txt831 # CHECK: vqneg.s8 d16, d16
833 # CHECK: vqneg.s16 d16, d16
835 # CHECK: vqneg.s32 d16, d16
837 # CHECK: vqneg.s8 q8, q8
839 # CHECK: vqneg.s16 q8, q8
841 # CHECK: vqneg.s32 q8, q8
/external/clang/include/clang/Basic/
Darm_neon.td792 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">;
942 def QNEG : SInst<"vqneg", "dd", "lQl">;
1565 def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">;
/external/vixl/src/aarch32/
Dassembler-aarch32.h5239 void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
5240 void vqneg(DataType dt, DRegister rd, DRegister rm) { vqneg(al, dt, rd, rm); } in vqneg() function
5242 void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
5243 void vqneg(DataType dt, QRegister rd, QRegister rm) { vqneg(al, dt, rd, rm); } in vqneg() function
Ddisasm-aarch32.h2087 void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
2089 void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
Dassembler-aarch32.cc21771 void Assembler::vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { in vqneg() function in vixl::aarch32::Assembler
21795 Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm); in vqneg()
21798 void Assembler::vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { in vqneg() function in vixl::aarch32::Assembler
21822 Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm); in vqneg()
Ddisasm-aarch32.cc5875 void Disassembler::vqneg(Condition cond, in vqneg() function in vixl::aarch32::Disassembler
5884 void Disassembler::vqneg(Condition cond, in vqneg() function in vixl::aarch32::Disassembler
27053 vqneg(CurrentCond(), in DecodeT32()
27119 vqneg(CurrentCond(), in DecodeT32()
41460 vqneg(al, dt, DRegister(rd), DRegister(rm)); in DecodeA32()
41512 vqneg(al, dt, QRegister(rd), QRegister(rm)); in DecodeA32()
Dmacro-assembler-aarch32.h8806 vqneg(cond, dt, rd, rm); in Vqneg()
8817 vqneg(cond, dt, rd, rm); in Vqneg()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td4280 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5651 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",