| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | neont2-reverse-encoding.s | 23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01]
26 vrev16.8 q8, q8
|
| D | neon-reverse-encoding.s | 23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3]
26 vrev16.8 q8, q8
|
| /external/llvm/test/MC/ARM/ |
| D | neon-reverse-encoding.s | 23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3]
26 vrev16.8 q8, q8
|
| D | neont2-reverse-encoding.s | 23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01]
26 vrev16.8 q8, q8
|
| /external/llvm/test/CodeGen/ARM/ |
| D | big-endian-neon-extend.ll | 6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
36 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
65 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
|
| D | popcnt.ll | 23 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
35 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
47 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
62 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
|
| D | big-endian-neon-trunc-store.ll | 18 ; CHECK: vrev16.8 [[REG]], [[REG]]
|
| D | vrev.ll | 101 ;CHECK: vrev16.8
109 ;CHECK: vrev16.8
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vrev.ll | 101 ;CHECK: vrev16.8
109 ;CHECK: vrev16.8
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5417 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
5418 void vrev16(DataType dt, DRegister rd, DRegister rm) { in vrev16() function
5419 vrev16(al, dt, rd, rm); in vrev16()
5422 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
5423 void vrev16(DataType dt, QRegister rd, QRegister rm) { in vrev16() function
5424 vrev16(al, dt, rd, rm); in vrev16()
|
| D | disasm-aarch32.h | 2182 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
2184 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
|
| D | assembler-aarch32.cc | 22683 void Assembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Assembler
22710 Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm); in vrev16()
22713 void Assembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Assembler
22740 Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm); in vrev16()
|
| D | disasm-aarch32.cc | 6124 void Disassembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Disassembler
6133 void Disassembler::vrev16(Condition cond, in vrev16() function in vixl::aarch32::Disassembler
26658 vrev16(CurrentCond(), in DecodeT32()
26685 vrev16(CurrentCond(), in DecodeT32()
41140 vrev16(al, dt, DRegister(rd), DRegister(rm)); in DecodeA32()
41162 vrev16(al, dt, QRegister(rd), QRegister(rm)); in DecodeA32()
|
| D | macro-assembler-aarch32.h | 9187 vrev16(cond, dt, rd, rm); in Vrev16()
9200 vrev16(cond, dt, rd, rm); in Vrev16()
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 868 # CHECK: vrev16.8 d16, d16
870 # CHECK: vrev16.8 q8, q8
|
| D | neon.txt | 977 # CHECK: vrev16.8 d16, d16
979 # CHECK: vrev16.8 q8, q8
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 868 # CHECK: vrev16.8 d16, d16
870 # CHECK: vrev16.8 q8, q8
|
| D | neon.txt | 977 # CHECK: vrev16.8 d16, d16
979 # CHECK: vrev16.8 q8, q8
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 785 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 4738 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4739 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 6319 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
6320 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
|