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Searched refs:vrev32 (Results 1 – 25 of 26) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-reverse-encoding.s15 @ CHECK: vrev32.8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x00]
16 vrev32.8 d16, d16
17 @ CHECK: vrev32.16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x00]
18 vrev32.16 d16, d16
19 @ CHECK: vrev32.8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x00]
20 vrev32.8 q8, q8
21 @ CHECK: vrev32.16 q8, q8 @ encoding: [0xf4,0xff,0xe0,0x00]
22 vrev32.16 q8, q8
Dneon-reverse-encoding.s15 @ CHECK: vrev32.8 d16, d16 @ encoding: [0xa0,0x00,0xf0,0xf3]
16 vrev32.8 d16, d16
17 @ CHECK: vrev32.16 d16, d16 @ encoding: [0xa0,0x00,0xf4,0xf3]
18 vrev32.16 d16, d16
19 @ CHECK: vrev32.8 q8, q8 @ encoding: [0xe0,0x00,0xf0,0xf3]
20 vrev32.8 q8, q8
21 @ CHECK: vrev32.16 q8, q8 @ encoding: [0xe0,0x00,0xf4,0xf3]
22 vrev32.16 q8, q8
/external/llvm/test/MC/ARM/
Dneon-reverse-encoding.s15 @ CHECK: vrev32.8 d16, d16 @ encoding: [0xa0,0x00,0xf0,0xf3]
16 vrev32.8 d16, d16
17 @ CHECK: vrev32.16 d16, d16 @ encoding: [0xa0,0x00,0xf4,0xf3]
18 vrev32.16 d16, d16
19 @ CHECK: vrev32.8 q8, q8 @ encoding: [0xe0,0x00,0xf0,0xf3]
20 vrev32.8 q8, q8
21 @ CHECK: vrev32.16 q8, q8 @ encoding: [0xe0,0x00,0xf4,0xf3]
22 vrev32.16 q8, q8
Dneont2-reverse-encoding.s15 @ CHECK: vrev32.8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x00]
16 vrev32.8 d16, d16
17 @ CHECK: vrev32.16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x00]
18 vrev32.16 d16, d16
19 @ CHECK: vrev32.8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x00]
20 vrev32.8 q8, q8
21 @ CHECK: vrev32.16 q8, q8 @ encoding: [0xf4,0xff,0xe0,0x00]
22 vrev32.16 q8, q8
/external/llvm/test/CodeGen/ARM/
Dbig-endian-neon-extend.ll21 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
51 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
68 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
70 ; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
82 ; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
97 ; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
Dbig-endian-neon-trunc-store.ll6 ; CHECK: vrev32.16 [[REG]], [[REG]]
8 ; CHECK: vrev32.16 [[REG]], [[REG2]]
20 ; CHECK: vrev32.8 [[REG]], [[REG2]]
Dvrev.ll69 ;CHECK: vrev32.8
77 ;CHECK: vrev32.16
85 ;CHECK: vrev32.8
93 ;CHECK: vrev32.16
127 ;CHECK: vrev32.16
183 ; CHECK: vrev32.8
Dbig-endian-neon-bitconv.ll191 ; CHECK: vrev32.8
201 ; CHECK: vrev32.8
212 ; CHECK: vrev32.16
222 ; CHECK: vrev32.16
296 ; CHECK: vrev32.8
306 ; CHECK: vrev32.8
317 ; CHECK: vrev32.16
327 ; CHECK: vrev32.16
Dpopcnt.ll51 ; CHECK: vrev32.16 {{d[0-9]+}}, {{d[0-9]+}}
66 ; CHECK: vrev32.16 {{q[0-9]+}}, {{q[0-9]+}}
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrev.ll69 ;CHECK: vrev32.8
77 ;CHECK: vrev32.16
85 ;CHECK: vrev32.8
93 ;CHECK: vrev32.16
127 ;CHECK: vrev32.16
155 ; CHECK: vrev32.16
/external/boringssl/linux-arm/crypto/sha/
Dsha1-armv4-large.S498 vrev32.8 q0,q0 @ yes, even on
499 vrev32.8 q1,q1 @ big-endian...
500 vrev32.8 q2,q2
502 vrev32.8 q3,q3
1195 vrev32.8 q0,q0
1216 vrev32.8 q1,q1
1247 vrev32.8 q2,q2
1278 vrev32.8 q3,q3
1345 vrev32.8 q4,q4
1346 vrev32.8 q5,q5
[all …]
/external/boringssl/linux-arm/crypto/chacha/
Dchacha-armv4.S871 vrev32.16 q3,q3
873 vrev32.16 q7,q7
875 vrev32.16 q11,q11
979 vrev32.16 q3,q3
981 vrev32.16 q7,q7
983 vrev32.16 q11,q11
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt860 # CHECK: vrev32.8 d16, d16
862 # CHECK: vrev32.16 d16, d16
864 # CHECK: vrev32.8 q8, q8
866 # CHECK: vrev32.16 q8, q8
Dneon.txt969 # CHECK: vrev32.8 d16, d16
971 # CHECK: vrev32.16 d16, d16
973 # CHECK: vrev32.8 q8, q8
975 # CHECK: vrev32.16 q8, q8
/external/libavc/encoder/arm/
Dime_distortion_metrics_a9q.s1064 vrev32.16 d0, d16 @I
1071 vrev32.16 q9, q7 @I Rearrange si's
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt860 # CHECK: vrev32.8 d16, d16
862 # CHECK: vrev32.16 d16, d16
864 # CHECK: vrev32.8 q8, q8
866 # CHECK: vrev32.16 q8, q8
Dneon.txt969 # CHECK: vrev32.8 d16, d16
971 # CHECK: vrev32.16 d16, d16
973 # CHECK: vrev32.8 q8, q8
975 # CHECK: vrev32.16 q8, q8
/external/boringssl/linux-arm/crypto/aes/
Dbsaes-armv7.S1399 vrev32.8 q0,q0
1401 vrev32.8 q4,q4
/external/vixl/src/aarch32/
Dassembler-aarch32.h5427 void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm);
5428 void vrev32(DataType dt, DRegister rd, DRegister rm) { in vrev32() function
5429 vrev32(al, dt, rd, rm); in vrev32()
5432 void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm);
5433 void vrev32(DataType dt, QRegister rd, QRegister rm) { in vrev32() function
5434 vrev32(al, dt, rd, rm); in vrev32()
Ddisasm-aarch32.h2186 void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm);
2188 void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm);
Dassembler-aarch32.cc22743 void Assembler::vrev32(Condition cond, in vrev32() function in vixl::aarch32::Assembler
22770 Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm); in vrev32()
22773 void Assembler::vrev32(Condition cond, in vrev32() function in vixl::aarch32::Assembler
22800 Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm); in vrev32()
Ddisasm-aarch32.cc6142 void Disassembler::vrev32(Condition cond, in vrev32() function in vixl::aarch32::Disassembler
6151 void Disassembler::vrev32(Condition cond, in vrev32() function in vixl::aarch32::Disassembler
26612 vrev32(CurrentCond(), in DecodeT32()
26639 vrev32(CurrentCond(), in DecodeT32()
41104 vrev32(al, dt, DRegister(rd), DRegister(rm)); in DecodeA32()
41126 vrev32(al, dt, QRegister(rd), QRegister(rm)); in DecodeA32()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td4719 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4720 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4722 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4723 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
/external/clang/include/clang/Basic/
Darm_neon.td784 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td6300 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
6301 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
6303 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
6304 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;

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