| /external/llvm/test/MC/ARM/ |
| D | neon-sub-encoding.s | 61 @ CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2]
62 vsubw.s8 q8, q8, d18
63 @ CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2]
64 vsubw.s16 q8, q8, d18
65 @ CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2]
66 vsubw.s32 q8, q8, d18
67 @ CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3]
68 vsubw.u8 q8, q8, d18
69 @ CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3]
70 vsubw.u16 q8, q8, d18
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | neon-sub-encoding.s | 35 @ CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2]
36 vsubw.s8 q8, q8, d18
37 @ CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2]
38 vsubw.s16 q8, q8, d18
39 @ CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2]
40 vsubw.s32 q8, q8, d18
41 @ CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3]
42 vsubw.u8 q8, q8, d18
43 @ CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3]
44 vsubw.u16 q8, q8, d18
[all …]
|
| /external/libavc/common/arm/ |
| D | ih264_iquant_itrans_recon_a9.s | 631 vsubw.s16 q12, q12, d6 @ y3 (0-3) 1+7-3
632 vsubw.s16 q13, q13, d7 @ y3 (0-7) 1+7-3
641 vsubw.s16 q12, q12, d12 @
642 vsubw.s16 q13, q13, d13 @
667 vsubw.s16 q10, q10, d14 @
668 vsubw.s16 q11, q11, d15 @
675 vsubw.s16 q10, q10, d14 @
676 vsubw.s16 q11, q11, d15 @
753 vsubw.s16 q12, q12, d6 @
754 vsubw.s16 q13, q13, d7 @
[all …]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vsub.ll | 223 ;CHECK: vsubw.s8
233 ;CHECK: vsubw.s16
243 ;CHECK: vsubw.s32
253 ;CHECK: vsubw.u8
263 ;CHECK: vsubw.u16
273 ;CHECK: vsubw.u32
|
| /external/arm-neon-tests/ |
| D | ref_vsubw.c | 26 #define INSN_NAME vsubw
|
| D | Android.mk | 36 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
|
| D | Makefile.gcc | 57 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
|
| D | Makefile | 51 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vsub.ll | 219 ;CHECK: vsubw.s8
229 ;CHECK: vsubw.s16
239 ;CHECK: vsubw.s32
249 ;CHECK: vsubw.u8
259 ;CHECK: vsubw.u16
269 ;CHECK: vsubw.u32
|
| /external/llvm/test/CodeGen/Hexagon/vect/ |
| D | vect-vsubw.ll | 2 ; CHECK: vsubw
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | loopfilter_16_neon.asm | 528 vsubw.u8 q15, d4 ; oq0 = op0 - p3
529 vsubw.u8 q15, d7 ; oq0 -= p0
534 vsubw.u8 q15, d5 ; oq1 = oq0 - p2
535 vsubw.u8 q15, d8 ; oq1 -= q0
540 vsubw.u8 q15, d6 ; oq2 = oq0 - p1
541 vsubw.u8 q15, d9 ; oq2 -= q1
|
| /external/libhevc/common/arm/ |
| D | ihevc_deblk_chroma_vert.s | 114 vsubw.u8 q2,q0,d4
|
| D | ihevc_deblk_luma_horz.s | 471 vsubw.s8 q2,q3,d8
524 vsubw.s8 q7,q7,d8
|
| D | ihevc_deblk_luma_vert.s | 554 vsubw.s8 q1,q1,d20
|
| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | xtype_alu.txt | 393 # CHECK: r17:16 = vsubw(r21:20, r31:30)
395 # CHECK: r17:16 = vsubw(r21:20, r31:30):sat
|
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | xtype_alu.ll | 1012 declare i64 @llvm.hexagon.A2.vsubw(i64, i64)
1014 %z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b)
1017 ; CHECK: = vsubw({{.*}}, {{.*}})
1024 ; CHECK: = vsubw({{.*}}, {{.*}}):sat
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | neon.txt | 1545 # CHECK: vsubw.s8 q8, q8, d18
1547 # CHECK: vsubw.s16 q8, q8, d18
1549 # CHECK: vsubw.s32 q8, q8, d18
1551 # CHECK: vsubw.u8 q8, q8, d18
1553 # CHECK: vsubw.u16 q8, q8, d18
1555 # CHECK: vsubw.u32 q8, q8, d18
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neon.txt | 1545 # CHECK: vsubw.s8 q8, q8, d18
1547 # CHECK: vsubw.s16 q8, q8, d18
1549 # CHECK: vsubw.s32 q8, q8, d18
1551 # CHECK: vsubw.u8 q8, q8, d18
1553 # CHECK: vsubw.u16 q8, q8, d18
1555 # CHECK: vsubw.u32 q8, q8, d18
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | v60Intrins.ll | 1333 %744 = call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> %742, <16 x i32> %743)
1641 %972 = call <32 x i32> @llvm.hexagon.V6.vsubw.dv(<32 x i32> %970, <32 x i32> %971)
2304 declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1
2538 declare <32 x i32> @llvm.hexagon.V6.vsubw.dv(<32 x i32>, <32 x i32>) #1
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5975 void vsubw(
5977 void vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { in vsubw() function
5978 vsubw(al, dt, rd, rn, rm); in vsubw()
|
| D | disasm-aarch32.h | 2473 void vsubw(
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 543 def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>;
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 930 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
938 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3637 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3638 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 4680 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4681 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
|