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/external/llvm/test/MC/Mips/msa/
Dtest_3r.s13 # CHECK: adds_s.w $w16, $w14, $w13 # encoding: [0x79,0x4d,0x74,0x10]
14 # CHECK: adds_s.d $w2, $w14, $w28 # encoding: [0x79,0x7c,0x70,0x90]
15 # CHECK: adds_u.b $w3, $w17, $w14 # encoding: [0x79,0x8e,0x88,0xd0]
21 # CHECK: addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce]
53 # CHECK: binsl.w $w14, $w15, $w13 # encoding: [0x7b,0x4d,0x7b,0x8d]
64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d]
69 # CHECK: ceq.w $w9, $w5, $w14 # encoding: [0x78,0x4e,0x2a,0x4f]
92 # CHECK: div_u.h $w24, $w21, $w14 # encoding: [0x7a,0xae,0xae,0x12]
93 # CHECK: div_u.w $w29, $w14, $w25 # encoding: [0x7a,0xd9,0x77,0x52]
96 # CHECK: dotp_s.w $w20, $w14, $w5 # encoding: [0x78,0x45,0x75,0x13]
[all …]
Dtest_3rf.s5 # CHECK: fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a]
10 # CHECK: fcle.d $w27, $w14, $w1 # encoding: [0x79,0xa1,0x76,0xda]
14 # CHECK: fcne.d $w14, $w20, $w15 # encoding: [0x78,0xef,0xa3,0x9c]
17 # CHECK: fcueq.w $w14, $w2, $w21 # encoding: [0x78,0xd5,0x13,0x9a]
56 # CHECK: fsne.d $w14, $w13, $w23 # encoding: [0x7a,0xf7,0x6b,0x9c]
62 # CHECK: fsueq.d $w18, $w14, $w14 # encoding: [0x7a,0xee,0x74,0x9a]
80 # CHECK: msubr_q.w $w1, $w14, $w20 # encoding: [0x7b,0xb4,0x70,0x5c]
88 fcaf.w $w14, $w11, $w25
93 fcle.d $w27, $w14, $w1
97 fcne.d $w14, $w20, $w15
[all …]
Dset-msa-directive.s4 # CHECK: addvi.b $w14, $w12, 14
8 # CHECK: subvi.b $w14, $w12, 14
14 addvi.b $w14, $w12, 14
19 subvi.b $w14, $w12, 14
Dtest_2rf.s22 # CHECK: frcp.d $w4, $w14 # encoding: [0x7b,0x2b,0x71,0x1e]
29 # CHECK: ftint_u.w $w20, $w14 # encoding: [0x7b,0x3a,0x75,0x1e]
55 frcp.d $w4, $w14
62 ftint_u.w $w20, $w14
Dtest_i5.s23 # CHECK: clti_u.b $w14, $w9, 29 # encoding: [0x79,0x9d,0x4b,0x87]
32 # CHECK: maxi_u.h $w1, $w14, 3 # encoding: [0x79,0xa3,0x70,0x46]
68 clti_u.b $w14, $w9, 29
77 maxi_u.h $w1, $w14, 3
Dtest_vec.s6 # CHECK: bsel.v $w8, $w0, $w14 # encoding: [0x78,0xce,0x02,0x1e]
14 bsel.v $w8, $w0, $w14
Dtest_i8.s11 # CHECK: shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82]
22 shf.w $w14, $w3, 93
/external/openssh/
Dblocks.c50 #define M(w0,w14,w9,w1) w0 = sigma1(w14) + w9 + sigma0(w1) + w0; argument
53 M(w0 ,w14,w9 ,w1 ) \
58 M(w5 ,w3 ,w14,w6 ) \
66 M(w13,w11,w6 ,w14) \
67 M(w14,w12,w7 ,w15) \
120 uint64 w14 = load_bigendian(in + 112); in crypto_hashblocks_sha512() local
137 F(w14,0x9bdc06a725c71235ULL) in crypto_hashblocks_sha512()
156 F(w14,0x06ca6351e003826fULL) in crypto_hashblocks_sha512()
175 F(w14,0xf40e35855771202aULL) in crypto_hashblocks_sha512()
194 F(w14,0xbef9a3f7b2c67915ULL) in crypto_hashblocks_sha512()
[all …]
/external/llvm/test/MC/AArch64/
Dneon-simd-copy.s10 ins v7.h[7], w14
15 mov v7.h[7], w14
34 smov w14, v6.h[4]
50 umov w14, v6.h[4]
112 dup v11.4h, w14
Darm64-arithmetic-encoding.s106 add w12, w13, w14
108 add w12, w13, w14, lsl #12
113 ; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b]
115 ; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b]
120 sub w12, w13, w14
122 sub w12, w13, w14, lsl #12
127 ; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b]
129 ; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b]
134 adds w12, w13, w14
136 adds w12, w13, w14, lsl #12
[all …]
Dtls-relocs.s63 movn w14, #:dtprel_g0:var
178 movz w14, #:gottprel_g1:var
265 movn w14, #:tprel_g0:var
/external/boringssl/linux-aarch64/crypto/sha/
Dsha1-armv8.S177 add w23,w23,w14 // future e+=X[i]
262 eor w6,w6,w14
335 eor w12,w12,w14
359 eor w14,w14,w16
363 eor w14,w14,w6
367 eor w14,w14,w11
370 ror w14,w14,#31
380 add w22,w22,w14 // future e+=X[i]
403 eor w17,w17,w14
459 eor w6,w6,w14
[all …]
Dsha256-armv8.S242 eor w14,w24,w24,ror#14
248 eor w16,w16,w14,ror#11 // Sigma1(e)
249 ror w14,w20,#2
256 eor w17,w14,w17,ror#13 // Sigma0(a)
263 ldp w13,w14,[x1],#2*4
310 rev w14,w14 // 11
320 add w24,w24,w14 // h+=X[i]
503 add w5,w5,w14
542 str w14,[sp,#12]
549 ror w14,w25,#2
[all …]
/external/libhevc/common/arm64/
Dihevc_intra_pred_chroma_horz.s196 ldrb w14,[x12],#1 //pu1_ref[two_nt]
197 sxtw x14,w14
200 dup v28.8b,w14
278 ldrb w14,[x12] //pu1_ref[two_nt]
279 sxtw x14,w14
288 dup v28.8b,w14
326 ldrb w14,[x12] //pu1_ref[two_nt]
327 sxtw x14,w14
333 dup v28.8b,w14
Dihevc_intra_pred_luma_horz.s196 ldrb w14,[x12],#1 //pu1_ref[two_nt]
197 sxtw x14,w14
202 dup v28.8b,w14
277 ldrb w14,[x12] //pu1_ref[two_nt]
278 sxtw x14,w14
285 dup v28.8b,w14
323 ldrb w14,[x12] //pu1_ref[two_nt]
324 sxtw x14,w14
330 dup v28.8b,w14
Dihevc_intra_pred_luma_mode_27_to_33.s153 umov w14, v5.s[0] //(i row)extract idx to the r register
154 sxtw x14,w14
202 umov w14, v5.s[1] //extract idx to the r register
203 sxtw x14,w14
282 umov w14, v3.s[0] //(i)extract idx to the r register
283 sxtw x14,w14
322 umov w14, v3.s[1] //extract idx to the r register
323 sxtw x14,w14
393 umov w14, v3.s[0] //(i)extract idx to the r register
394 sxtw x14,w14
Dihevc_sao_edge_offset_class0.s158 … LDRB w14,[x6,x5] //pu1_src_org[(ht - row) * src_strd + 16 - 1 + (wd - col)]
166 … STRB w14,[x2],#1 //pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)]
191 …LDRB w14,[x6,x5] //II pu1_src_org[(ht - row) * src_strd + 16 - 1 + (wd - co…
196 …STRB w14,[x2],#1 //II pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row…
329 LDRB w14,[x6, x11] //pu1_src_org[(ht - row) * src_strd + (wd - 1)]
330 … STRB w14,[x2],#1 //pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)]
Dihevc_intra_pred_filters_luma_mode_19_to_25.s265 umov w14, v5.s[0] //(i row)extract idx to the r register
266 sxtw x14,w14
311 umov w14, v5.s[1] //extract idx to the r register
312 sxtw x14,w14
388 umov w14, v3.s[0] //(i)extract idx to the r register
389 sxtw x14,w14
430 umov w14, v3.s[1] //extract idx to the r register
431 sxtw x14,w14
501 umov w14, v3.s[0] //(i)extract idx to the r register
502 sxtw x14,w14
Dihevc_sao_edge_offset_class0_chroma.s187 LDRH w14,[x6,x5] //pu1_src_org[(ht - row) * src_strd + 14 + (wd - col)]
199 … STRH w14,[x2],#2 //pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)]
288 … LDRH w14,[x6,x5] //II pu1_src_org[(ht - row) * src_strd + 14 + (wd - col)]
291 …STRH w14,[x2],#2 //II pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row…
380 LDRH w14,[x6, x5] //pu1_src_org[(ht - row) * 2* src_strd + (wd - 2)]
386 …STRH w14,[x2],#2 //pu1_src_left[(ht - row) * 2] = au1_src_left_tmp[(ht - ro…
453 LDRH w14,[x6, x5] //II pu1_src_org[(ht - row) * 2* src_strd + (wd - 2)]
460 …STRH w14,[x2],#2 //II pu1_src_left[(ht - row) * 2] = au1_src_left_tmp[(ht -…
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt13 0x79 0x4d 0x74 0x10 # CHECK: adds_s.w $w16, $w14, $w13
14 0x79 0x7c 0x70 0x90 # CHECK: adds_s.d $w2, $w14, $w28
15 0x79 0x8e 0x88 0xd0 # CHECK: adds_u.b $w3, $w17, $w14
21 0x78 0x4e 0x5c 0xce # CHECK: addv.w $w19, $w11, $w14
53 0x7b 0x4d 0x7b 0x8d # CHECK: binsl.w $w14, $w15, $w13
64 0x7a 0x26 0x63 0x8d # CHECK: bset.h $w14, $w12, $w6
69 0x78 0x4e 0x2a 0x4f # CHECK: ceq.w $w9, $w5, $w14
92 0x7a 0xae 0xae 0x12 # CHECK: div_u.h $w24, $w21, $w14
93 0x7a 0xd9 0x77 0x52 # CHECK: div_u.w $w29, $w14, $w25
96 0x78 0x45 0x75 0x13 # CHECK: dotp_s.w $w20, $w14, $w5
[all …]
Dtest_3rf.txt5 0x78 0x19 0x5b 0x9a # CHECK: fcaf.w $w14, $w11, $w25
10 0x79 0xa1 0x76 0xda # CHECK: fcle.d $w27, $w14, $w1
14 0x78 0xef 0xa3 0x9c # CHECK: fcne.d $w14, $w20, $w15
17 0x78 0xd5 0x13 0x9a # CHECK: fcueq.w $w14, $w2, $w21
56 0x7a 0xf7 0x6b 0x9c # CHECK: fsne.d $w14, $w13, $w23
62 0x7a 0xee 0x74 0x9a # CHECK: fsueq.d $w18, $w14, $w14
80 0x7b 0xb4 0x70 0x5c # CHECK: msubr_q.w $w1, $w14, $w20
/external/boringssl/linux-aarch64/crypto/chacha/
Dchacha-armv8.S100 add w14,w14,w19
104 eor w10,w10,w14
124 add w14,w14,w19
128 eor w10,w10,w14
150 add w14,w14,w20
154 eor w9,w9,w14
174 add w14,w14,w20
178 eor w9,w9,w14
411 add w14,w14,w19
419 eor w10,w10,w14
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-arithmetic.txt97 # CHECK: add w12, w13, w14
99 # CHECK: add w12, w13, w14, lsl #12
101 # CHECK: add w12, w13, w14, lsr #10
103 # CHECK: add w12, w13, w14, asr #7
115 # CHECK: sub w12, w13, w14
117 # CHECK: sub w12, w13, w14, lsl #12
119 # CHECK: sub w12, w13, w14, lsr #10
121 # CHECK: sub w12, w13, w14, asr #7
133 # CHECK: adds w12, w13, w14
135 # CHECK: adds w12, w13, w14, lsl #12
[all …]
/external/libmpeg2/common/armv8/
Dimpeg2_format_conv.s136 ldr w14, [sp, #112] //// Load convert_uv_only
138 cmp w14, #1
308 ldr w14, [sp, #112] //// Load convert_uv_only
310 cmp w14, #1
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-msa.s12 …fclass.d $w14,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
19 …ffint_s.w $w16,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
40 …ftint_s.w $w27,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
53 …nlzc.d $w14,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…

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