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Searched refs:wzr (Results 1 – 25 of 88) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s38 add w30, w29, wzr, uxtw
83 sub w30, w29, wzr, uxtw
118 adds w30, w29, wzr, uxtw
122 adds wzr, w2, w3, sxtw
153 subs w30, w29, wzr, uxtw
157 subs wzr, w2, w3, sxtw
188 cmp w29, wzr, uxtw
224 cmn w29, wzr, uxtw
243 cmn wsp, wzr, sxtw
253 adds wzr, wsp, w3, lsl #4
[all …]
Darm64-aliases.s29 orr w2, wzr, w9
43 ands wzr, w1, w2, lsl #2
90 cmp wzr, w1
103 ; CHECK: cmp wzr, w1 ; encoding: [0xff,0x03,0x01,0x6b]
142 mov wzr, #0xffffffff
143 mov wzr, #0xffffff00
147 ; CHECK: mov wzr, #-0x1
148 ; CHECK: mov wzr, #-0x100
191 orr w15, wzr, #0xaaaaaaaa
199 orr w3, wzr, #0x1
[all …]
Darm64-bitfield-encoding.s14 sbfiz wzr, w0, #31, #1
16 ubfiz wzr, w0, #31, #1
25 ; CHECK: sbfiz wzr, w0, #31, #1 ; encoding: [0x1f,0x00,0x01,0x13]
27 ; CHECK: lsl wzr, w0, #31 ; encoding: [0x1f,0x00,0x01,0x53]
Darm64-basic-a64-instructions.s4 crc32h w28, wzr, w30
9 crc32cw wzr, w3, w5
Dbasic-a64-diagnostics.s116 add wzr, w20, #0x123
117 add w20, wzr, #0x321
118 add wzr, wzr, #0xfff
149 adds w4, wzr, #0x123
397 cmn w19, wzr, asr #-1
398 cmn wzr, wzr, asr #32
446 cmp w19, wzr, asr #-1
447 cmp wzr, wzr, asr #32
495 neg w19, wzr, asr #-1
496 neg wzr, wzr, asr #32
[all …]
Dcyclone-crc.s5 crc32w w19, wzr, w20
12 CHECK: crc32w w19, wzr, w20
/external/llvm/test/CodeGen/AArch64/
Dmovw-consts.ll12 ; CHECK: orr w0, wzr, #0x1
18 ; CHECK: orr w0, wzr, #0xffff
24 ; CHECK: orr w0, wzr, #0x10000
30 ; CHECK: orr w0, wzr, #0xffff0000
78 ; CHECK: str wzr
85 ; CHECK: orr {{w[0-9]+}}, wzr, #0x1
92 ; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
99 ; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
106 ; CHECK: orr {{w[0-9]+}}, wzr, #0xffff0000
Darm64-patchpoint-webkit_jscc.ll44 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
46 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
48 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
58 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
80 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
82 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6
84 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
86 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
96 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
98 ; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8
Dbswap-known-bits.ll7 ; CHECK: orr w0, wzr, #0x1
17 ; CHECK: orr w0, wzr, #0x1
27 ; CHECK: orr w0, wzr, #0x1
37 ; CHECK: orr w0, wzr, #0x1
Darm64-fast-isel-store.ll6 ; CHECK: strb wzr, [x0]
13 ; CHECK: strh wzr, [x0]
20 ; CHECK: str wzr, [x0]
Dswifterror.ll12 ; CHECK-APPLE: orr w0, wzr, #0x10
14 ; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
20 ; CHECK-O0: orr w{{.*}}, wzr, #0x10
23 ; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
121 ; CHECK-APPLE: orr w0, wzr, #0x10
123 ; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
133 ; CHECK-O0: orr w{{.*}}, wzr, #0x10
136 ; CHECK-O0: orr [[ID2:w[0-9]+]], wzr, #0x1
165 ; CHECK-APPLE: orr w0, wzr, #0x10
177 ; CHECK-O0: orr w{{.*}}, wzr, #0x10
[all …]
Dfast-isel-addressing-modes.ll56 ; CHECK: strb wzr, [x0]
70 ; CHECK: strb wzr, [x0]
77 ; CHECK: strh wzr, [x0]
84 ; CHECK: str wzr, [x0]
98 ; CHECK: str wzr, [x0]
113 ; CHECK: orr {{w|x}}[[REG:[0-9]+]], {{wzr|xzr}}, #0x80
176 ; SDAG: orr w[[NUM:[0-9]+]], wzr, #0x4000
190 ; CHECK: stur wzr, [x0, #-256]
201 ; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
211 ; CHECK: stur wzr, [x0, #255]
[all …]
Dcmpxchg-idioms.ll15 ; CHECK: orr w0, wzr, #0x1
20 ; CHECK: mov w0, wzr
42 ; CHECK: orr [[TMP:w[0-9]+]], wzr, #0x1
48 ; CHECK: mov [[TMP:w[0-9]+]], wzr
Darm64-csel.ll115 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
126 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
137 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
148 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
181 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
192 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
203 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
214 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
Darm64-coalescing-MOVi32imm.ll3 ; CHECK: orr w0, wzr, #0x1
5 ; CHECK-NEXT: orr w0, wzr, #0x1
Di128-align.ll16 ; CHECK: {{movz x0, #48|orr w0, wzr, #0x30}}
28 ; CHECK: {{movz x0, #16|orr w0, wzr, #0x10}}
Dremat-float0.ll10 ; CHECK: fmov s0, wzr
12 ; CHECK: fmov s0, wzr
Darm64-long-shift.ll5 ; CHECK: orr w[[SIXTY_FOUR:[0-9]+]], wzr, #0x40
26 ; CHECK: orr w[[SIXTY_FOUR:[0-9]+]], wzr, #0x40
48 ; CHECK: orr w[[SIXTY_FOUR:[0-9]+]], wzr, #0x40
Dcmp-const-max.ll17 ; CHECK-NEXT: mov w0, wzr
34 ; CHECK-NEXT: mov w0, wzr
Darm64-regress-opt-cmp.mir4 # CHECK-NEXT: %wzr = SUBSWri {{.*}}
31 %wzr = SUBSWri killed %1, 0, 0, implicit-def %nzcv
Dmachine_cse_impdef_killflags.ll8 ; CHECK-DAG: mov [[REG0:w[0-9]+]], wzr
9 ; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
Darm64-memset-inline.ll6 ; CHECK: str wzr, [x0, #8]
15 ; CHECK: strh wzr, [sp, #32]
Darm64-fast-isel-fcmp.ll38 ; CHECK: mov {{w[0-9]+}}, wzr
87 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, le
112 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, vc
159 ; CHECK: orr {{w[0-9]+}}, wzr, #0x1
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt83 # CHECK: add wzr, w3, w5
84 # CHECK: add w20, wzr, w4
85 # CHECK: add w4, w6, wzr
87 # CHECK: add w9, w3, wzr, lsl #10
138 # CHECK: adds w20, wzr, w4
139 # CHECK: adds w4, w6, wzr
141 # CHECK: adds w9, w3, wzr, lsl #10
191 # CHECK: sub wzr, w3, w5
192 # CHECK: {{sub w20, wzr, w4|neg w20, w4}}
193 # CHECK: sub w4, w6, wzr
[all …]
Darm64-crc32.txt4 # CHECK: crc32h w28, wzr, w30
9 # CHECK: crc32cw wzr, w3, w5

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