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/external/libhevc/common/arm64/
Dihevc_inter_pred_chroma_horz_w16out.s132 sub x12,x0,#2 //pu1_src - 2
134 add x4,x12,x2 //pu1_src_tmp2_8 = pu1_src + src_strd
174 add x4,x12,x2
177 and x0, x12, #31
178 add x20,x12, x2 , lsl #1
186 add x19,x12,#8
187 ld1 { v0.2s},[x12],x11 //vector load pu1_src
191 ld1 { v2.2s},[x12],x11 //vector load pu1_src
196 ld1 { v4.2s},[x12],x11 //vector load pu1_src
201 ld1 { v6.2s},[x12],x9 //vector load pu1_src
[all …]
Dihevc_inter_pred_filters_luma_horz.s145 sub x12,x0,#3 //pu1_src - 3
147 add x4,x12,x2 //pu1_src_tmp2_8 = pu1_src + src_strd
186 sub x12,x0,#3 //pu1_src - 3
190 add x12, x12,#16
198 add x4,x12,x2 //pu1_src + src_strd
204 ld1 {v0.2s},[x12],x11 //vector load pu1_src
205 ld1 {v1.2s},[x12],x11
206 ld1 {v2.2s},[x12],x11
207 ld1 {v3.2s},[x12],x11
228 ld1 {v4.2s},[x12],x11
[all …]
Dihevc_inter_pred_chroma_horz.s132 sub x12,x0,#2 //pu1_src - 2
134 add x4,x12,x2 //pu1_src_tmp2_8 = pu1_src + src_strd
164 add x4,x12,x2
166 and x0, x12, #31
169 add x20,x12, x2 , lsl #1
174 add x19,x12,#8
175 ld1 { v0.2s},[x12],x11 //vector load pu1_src
180 ld1 { v2.2s},[x12],x11 //vector load pu1_src
183 ld1 { v4.2s},[x12],x11 //vector load pu1_src
186 ld1 { v6.2s},[x12],x9 //vector load pu1_src
[all …]
Dihevc_intra_pred_chroma_horz.s104 add x12,x0,x6 //*pu1_ref[four_nt]
114 sub x12,x12,#16 //move to 16th value pointer
118 ld1 { v0.8h},[x12] //load 16 values. d1[7] will have the 1st value.
119 sub x12,x12,#16
120 ld1 { v18.8h},[x12] //load 16 values. d1[7] will have the 1st value.
176 sub x12,x12,#16 //move to 16th value pointer
196 ldrb w14,[x12],#1 //pu1_ref[two_nt]
201 sub x12,x12,#17
202 ld1 { v0.16b},[x12]
204 sub x12,x12,#16
[all …]
Dihevc_intra_pred_luma_horz.s107 add x12,x0,x6 //*pu1_ref[two_nt]
116 sub x12,x12,#16 //move to 16th value pointer
120 ld1 { v0.16b},[x12] //load 16 values. d1[7] will have the 1st value.
176 sub x12,x12,#16 //move to 16th value pointer
196 ldrb w14,[x12],#1 //pu1_ref[two_nt]
198 ld1 { v30.8b},[x12],#8 //pu1_ref[two_nt + 1 + col]
199 ld1 { v31.8b},[x12] //pu1_ref[two_nt + 1 + col]
200 sub x12,x12,#8
203 sub x12,x12,#17
204 ld1 { v0.16b},[x12]
[all …]
Dihevc_sao_edge_offset_class0_chroma.s123 MOV x12,x9 //Move wd to x12 for loop count
127 SUBS x12,x12,#8 //Decrement the loop counter by 8
149 MOV x12,#-1 //move -1 to x12
160 MOV x12,x0 //pu1_src_cpy = pu1_src
165 LD1 {v19.16b},[x12],x1 //pu1_cur_row = vld1q_u8(pu1_src_cpy)
174 LD1 {v30.16b},[x12] //II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
178 SUB x12,x12,x1
191 LDRB w11,[x12,#16] //pu1_src_cpy[16]
197 LDRB w11,[x12,#17] //pu1_src_cpy[17]
201 ADD x12,x12,x1
[all …]
Dihevc_intra_pred_filters_chroma_mode_19_to_25.s185 mov x12, #-1
187 sub x20, x9, x12 //count to take care off ref_idx
232 mov x12,x4
238 lsr x12, x4, #4 //divide by 8
241 mul x7, x4, x12
274 add x12,x8,x9 //(ii)*pu1_ref[ref_main_idx]
280 ld1 {v12.8b},[x12],x11 //(ii)ref_main_idx
283 ld1 {v13.8b},[x12] //(ii)ref_main_idx_1
292 add x12,x8,x9 //(iv)*pu1_ref[ref_main_idx]
300 ld1 {v20.8b},[x12],x11 //(iv)ref_main_idx
[all …]
Dihevc_deblk_luma_horz.s130 and x12,x12,#0xff
135 add x12,x12,x2
136 subs x9,x12,x9,lsl #1 // dq0 value is stored in x9
164 add x12,x12,x4
165 subs x12,x12,x3,lsl #1 // dq3value is stored in x12
166 csneg x12,x12,x12,pl
178 add x4,x11,x12 // x4 has the d3 value
185 add x12,x12,x9 // x12 has the value dq
360 cmp x8,x12
375 cmp x8,x12
[all …]
Dihevc_sao_edge_offset_class0.s103 MOV x12,x9 //Move wd to x12 for loop count
111 SUBS x12,x12,#8 //Decrement the loop counter by 8
130 MOV x12,#0xFF //move -1 to x12
140 MOV x12,x0 //pu1_src_cpy = pu1_src
145 LD1 {v17.16b},[x12],x1 //pu1_cur_row = vld1q_u8(pu1_src_cpy)
152 LD1 {v26.16b},[x12] //II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
164 SUB x12,x12,x1 //Decrement the pu1_src pointer by src_strd
168 LDRB w11,[x12,#16] //pu1_src_cpy[16]
172 ADD x12,x12,x1 //Increment the pu1_src pointer by src_strd
176 LDRB w11,[x12,#16] //II pu1_src_cpy[16]
[all …]
Dihevc_intra_pred_luma_mode_27_to_33.s124 mov x12,x4
130 lsr x12, x4, #3 //divide by 8
133 mul x7, x4, x12
167 add x12,x8,x9 //(ii)*pu1_ref[ref_main_idx]
173 ld1 {v12.8b},[x12],x11 //(ii)ref_main_idx
176 ld1 {v13.8b},[x12] //(ii)ref_main_idx_1
186 add x12,x8,x9 //(iv)*pu1_ref[ref_main_idx]
194 ld1 {v20.8b},[x12],x11 //(iv)ref_main_idx
197 ld1 {v21.8b},[x12] //(iv)ref_main_idx_1
226 add x12,x8,x9 //(vi)*pu1_ref[ref_main_idx]
[all …]
Dihevc_intra_pred_chroma_mode_27_to_33.s119 mov x12,x4
127 lsr x12, x4, #4 //divide by 8
130 mul x7, x4, x12
162 add x12,x8,x9 //(ii)*pu1_ref[ref_main_idx]
168 ld1 {v12.8b},[x12],x11 //(ii)ref_main_idx
171 ld1 {v13.8b},[x12] //(ii)ref_main_idx_1
181 add x12,x8,x9 //(iv)*pu1_ref[ref_main_idx]
189 ld1 {v20.8b},[x12],x11 //(iv)ref_main_idx
192 ld1 {v21.8b},[x12] //(iv)ref_main_idx_1
221 add x12,x8,x9 //(vi)*pu1_ref[ref_main_idx]
[all …]
Dihevc_intra_pred_filters_luma_mode_19_to_25.s192 mov x12, #-1
194 sub x20, x9, x12 //count to take care off ref_idx
236 mov x12,x4
242 lsr x12, x4, #3 //divide by 8
245 mul x7, x4, x12
277 add x12,x8,x9 //(ii)*pu1_ref[ref_main_idx]
283 ld1 {v12.8b},[x12],x11 //(ii)ref_main_idx
286 ld1 {v13.8b},[x12] //(ii)ref_main_idx_1
295 add x12,x8,x9 //(iv)*pu1_ref[ref_main_idx]
303 ld1 {v20.8b},[x12],x11 //(iv)ref_main_idx
[all …]
Dihevc_inter_pred_chroma_copy.s103 LSL x12,x6,#1 //wd << 1
108 TST x12,#15 //checks wd for multiples for 16
110 TST x12,#7 //checks wd for multiples for 4 & 8
112 SUB x11,x12,#4
117 SUBS x4,x12,#0 //checks wd == 0
148 SUBS x4,x12,#0 //checks wd == 0
165 SUB x11,x12,#8
170 SUBS x4,x12,#0 //checks wd
198 SUBS x4,x12,#0 //checks wd
211 SUB x11,x12,#16
[all …]
Dihevc_sao_edge_offset_class2.s105 ADD x12,sp,#0x02 //temp array
110 …ST1 {v0.8b},[x12],#8 //au1_src_top_tmp[col] = pu1_src[(ht - 1) * src_strd + col]
122 SUBS x12,x9,x11 //pu1_src[0] - pu1_src_top_left[0]
126 csel x12, x20, x12,LT
128 csel x12, x20, x12,GT //SIGN(pu1_src[0] - pu1_src_top_left[0])
138 …ADD x4,x12,x11 //SIGN(pu1_src[0] - pu1_src_top_left[0]) + SIGN(pu1_src[0…
141 LDRSB x12,[x14,x4] //edge_idx = gi1_table_edge_idx[edge_idx]
142 CMP x12,#0 //0 != edge_idx
144 LDRSB x10,[x6,x12] //pi1_sao_offset[edge_idx]
158 madd x12, x11, x1, x10 //wd - 1 + (ht - 1) * src_strd
[all …]
Dihevc_sao_edge_offset_class2_chroma.s119 ADD x12,sp,#10 //temp array
124 …ST1 {v0.8b},[x12],#8 //au1_src_top_tmp[col] = pu1_src[(ht - 1) * src_strd + col]
137 SUB x12,x9,x11 //pu1_src[0] - pu1_src_top_left[0]
140 CMP x12,#0
143 csel x12, x20, x12,LT
147 csel x12, x20, x12,GT //SIGN(pu1_src[0] - pu1_src_top_left[0])
157 …ADD x11,x12,x11 //SIGN(pu1_src[0] - pu1_src_top_left[0]) + SIGN(pu1_src[0…
160 LDRSB x12,[x14,x11] //edge_idx = gi1_table_edge_idx[edge_idx]
161 CMP x12,#0 //0 != edge_idx
163 LDRSB x11,[x6,x12] //pi1_sao_offset_u[edge_idx]
[all …]
Dihevc_inter_pred_chroma_copy_w16out.s115 mov x12,x17 //loads wd
116 lsl x12,x12,#1 //2*wd
125 tst x12,#7 //conditional check for wd (multiples)
129 sub x11,x12,#4
136 subs x4,x12,#0 //wd conditional subtract
180 subs x4,x12,#0 //wd conditional subtract
207 sub x20,x12,x3, lsl #2 // x11 = (dst_strd * 4) - width
209 sub x20,x12,x2,lsl #2 //x2->src_strd
211 lsr x4, x12, #3 // divide by 8
214 sub x4,x12,#0 //wd conditional check
[all …]
Dihevc_weighted_pred_bi_default.s194 …add x12,x1,x4 //pi2_src_tmp2 = pi2_src2 + 2*src_strd2(2* because pi2_src…
201 ld1 {v3.4h},[x12],x4 //load and increment the pi2_src2 ii iteration
207 ld1 {v23.4h},[x12],x4 //load and increment the pi2_src2 iii iteration
211 ld1 {v25.4h},[x12],x4 //load and increment the pi2_src2 iv iteration
249 …add x12,x1,x4 //pi2_src_tmp2 = pi2_src2 + 2*src_strd2(2* because pi2_src…
256 ld1 {v3.4h},[x12],x4 //load and increment the pi2_src2 ii iteration
289 …add x12,x1,x4 //pi2_src_tmp2 = pi2_src2 + 2*src_strd2(2* because pi2_src…
298 ld1 { v30.8h},[x12],x4 //load and increment the pi2_src2 ii iteration
301 ld1 { v18.8h},[x12],x4 //load and increment the pi2_src2 iii iteration
307 ld1 { v29.8h},[x12],x4 //load and increment the pi2_src2 iv iteration
[all …]
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s20 add x12, x1, w20, uxtw
66 sub x12, x1, w20, uxtw
101 adds x12, x1, w20, uxtw
136 subs x12, x1, w20, uxtw
241 cmp x12, x13, uxtx #4
659 cmn x12, x13, lsr #0
719 cmp x12, x13, lsr #0
786 neg x12, x11, asr #31
844 negs x12, x11, asr #31
1492 rev64 x13, x12
[all …]
Dbasic-a64-diagnostics.s401 cmn x11, x12, lsr #-1
402 cmn x11, x12, lsr #64
450 cmp x11, x12, lsr #-1
451 cmp x11, x12, lsr #64
499 neg x11, x12, lsr #-1
500 neg x11, x12, lsr #64
548 negs x11, x12, lsr #-1
549 negs x11, x12, lsr #64
845 uxtb x3, x12
1901 ldur x12, [sp, #256]
[all …]
/external/pcre/dist2/src/
Dpcre2_chartables.c.dist173 0x00,0x1a,0x1a,0x1a,0x1a,0x1a,0x1a,0x12, /* @ - G */
174 0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12, /* H - O */
175 0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12, /* P - W */
176 0x12,0x12,0x12,0x80,0x80,0x00,0x80,0x10, /* X - _ */
177 0x00,0x1a,0x1a,0x1a,0x1a,0x1a,0x1a,0x12, /* ` - g */
178 0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12, /* h - o */
179 0x12,0x12,0x12,0x12,0x12,0x12,0x12,0x12, /* p - w */
180 0x12,0x12,0x12,0x80,0x80,0x00,0x00,0x00, /* x -127 */
/external/boringssl/linux-aarch64/crypto/bn/
Darmv8-mont.S62 adds x12,x16,x13
67 adds x12,x12,x6
71 str x12,[x22],#8 // tp[j-1]
79 adds x12,x16,x13
83 adds x12,x12,x6
88 stp x12,x13,[x22]
124 adds x12,x16,x13
134 adds x12,x12,x6
136 str x12,[x22,#-16] // tp[j-1]
146 adds x12,x16,x13
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt329 # CHECK: cmn x12, x13, lsr #0
379 # CHECK: cmp x12, x13, lsr #0
434 # CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31
484 # CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31
1027 0x12 0x08 0xc0 0x5a
1060 0x12 0x5e 0xdf 0x9a
1167 # CHECK: smaddl xzr, w10, w11, x12
1178 # CHECK: smsubl xzr, w10, w11, x12
1189 # CHECK: umaddl xzr, w10, w11, x12
1200 # CHECK: umsubl xzr, w10, w11, x12
[all …]
/external/llvm/test/MC/Disassembler/Lanai/
Dv11.txt5 0x0a 0xc4 0x12 0x34
7 0x0a 0xc5 0x12 0x34
11 0x0a 0xc6 0x12 0x34
13 0x0a 0xc7 0x12 0x34
25 0x1a 0xc4 0x12 0x34
27 0x1a 0xc5 0x12 0x34
31 0x1a 0xc6 0x12 0x34
33 0x1a 0xc7 0x12 0x34
35 0x4a 0xc4 0x12 0x34
37 0x4a 0xc5 0x12 0x34
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/
Dmblaze_fpu.txt29 0x58 0x01 0x12 0x00
32 0x58 0x01 0x12 0x10
35 0x58 0x01 0x12 0x20
38 0x58 0x01 0x12 0x30
41 0x58 0x01 0x12 0x40
44 0x58 0x01 0x12 0x50
47 0x58 0x01 0x12 0x60
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-arm-neg.txt6 [0x44,0x0d,0x12,0xf2]
15 [0x12,0x0d,0x11,0xf3]
16 [0x54,0x0d,0x12,0xf3]
25 [0x12,0x0d,0x11,0xf2]
26 [0x54,0x0d,0x12,0xf2]
35 [0x12,0x0d,0x31,0xf2]
45 [0x12,0x0c,0x11,0xf2]
46 [0x54,0x0c,0x12,0xf2]
50 [0x12,0x0c,0x31,0xf2]
95 [0x12,0x0e,0x11,0xf3]
[all …]

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