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Searched refs:MVEA_CR_SPE_ZERO_THRESH (Results 1 – 3 of 3) sorted by relevance

/hardware/intel/img/psb_video/src/hwdefs/
DtopazSC_defs.h106 #define MVEA_CR_SPE_ZERO_THRESH 0x0370 macro
Dmvea_regs.h1166 #define MVEA_CR_SPE_ZERO_THRESH 0x0370 macro
/hardware/intel/img/psb_video/src/
Dpnw_hostcode.c202 pnw_cmdbuf_insert_reg_write(MVEARegBase[i32Core], MVEA_CR_SPE_ZERO_THRESH, SPE_ZERO_THRESHOLD); in LoadMPEG4Bias()
259 pnw_cmdbuf_insert_reg_write(MVEARegBase[i32Core], MVEA_CR_SPE_ZERO_THRESH, SPE_ZERO_THRESHOLD); in LoadH263Bias()
366 pnw_cmdbuf_insert_reg_write(MVEARegBase[i32Core], MVEA_CR_SPE_ZERO_THRESH, 0); in LoadH264Bias()