1// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s 2// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s 3// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI %s 4 5//===----------------------------------------------------------------------===// 6// Instructions 7//===----------------------------------------------------------------------===// 8 9s_movk_i32 s2, 0x6 10// GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0] 11 12s_cmovk_i32 s2, 0x6 13// SICI: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1] 14// VI: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb0] 15 16s_cmpk_eq_i32 s2, 0x6 17// SICI: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1] 18// VI: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1] 19 20s_cmpk_lg_i32 s2, 0x6 21// SICI: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2] 22// VI: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1] 23 24s_cmpk_gt_i32 s2, 0x6 25// SICI: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2] 26// VI: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2] 27 28s_cmpk_ge_i32 s2, 0x6 29// SICI: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3] 30// VI: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2] 31 32s_cmpk_lt_i32 s2, 0x6 33// SICI: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3] 34// VI: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3] 35 36s_cmpk_le_i32 s2, 0x6 37// SICI: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4] 38// VI: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3] 39 40s_cmpk_eq_u32 s2, 0x6 41// SICI: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4] 42// VI: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4] 43 44s_cmpk_lg_u32 s2, 0x6 45// SICI: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5] 46// VI: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4] 47 48s_cmpk_gt_u32 s2, 0x6 49// SICI: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5] 50// VI: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5] 51 52s_cmpk_ge_u32 s2, 0x6 53// SICI: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6] 54// VI: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5] 55 56s_cmpk_lt_u32 s2, 0x6 57// SICI: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6] 58// VI: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6] 59 60s_cmpk_le_u32 s2, 0x6 61// SICI: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7] 62// VI: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6] 63 64s_addk_i32 s2, 0x6 65// SICI: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7] 66// VI: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7] 67 68s_mulk_i32 s2, 0x6 69// SICI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8] 70// VI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7] 71 72s_cbranch_i_fork s[2:3], 0x6 73// SICI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8] 74// VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8] 75 76// raw number mapped to known HW register 77s_getreg_b32 s2, 0x6 78// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9] 79// VI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8] 80 81// HW register identifier, non-default offset/width 82s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) 83// SICI: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x02,0xb9] 84// VI: s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) ; encoding: [0x45,0xf0,0x82,0xb8] 85 86// HW register code of unknown HW register, non-default offset/width 87s_getreg_b32 s2, hwreg(51, 1, 31) 88// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9] 89// VI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8] 90 91// HW register code of unknown HW register, default offset/width 92s_getreg_b32 s2, hwreg(51) 93// SICI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x02,0xb9] 94// VI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8] 95 96// raw number mapped to known HW register 97s_setreg_b32 0x6, s2 98// SICI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x82,0xb9] 99// VI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9] 100 101// raw number mapped to unknown HW register 102s_setreg_b32 0x33, s2 103// SICI: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x82,0xb9] 104// VI: s_setreg_b32 hwreg(51, 0, 1), s2 ; encoding: [0x33,0x00,0x02,0xb9] 105 106// raw number mapped to known HW register, default offset/width 107s_setreg_b32 0xf803, s2 108// SICI: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x82,0xb9] 109// VI: s_setreg_b32 hwreg(HW_REG_TRAPSTS), s2 ; encoding: [0x03,0xf8,0x02,0xb9] 110 111// HW register identifier, default offset/width implied 112s_setreg_b32 hwreg(HW_REG_HW_ID), s2 113// SICI: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x82,0xb9] 114// VI: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x02,0xb9] 115 116// HW register identifier, non-default offset/width 117s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 118// SICI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9] 119// VI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9] 120 121// HW register code, non-default offset/width 122s_setreg_b32 hwreg(5, 1, 31), s2 123// SICI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x82,0xb9] 124// VI: s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 ; encoding: [0x45,0xf0,0x02,0xb9] 125 126// raw number mapped to known HW register 127s_setreg_imm32_b32 0x6, 0xff 128// SICI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] 129// VI: s_setreg_imm32_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] 130 131// HW register identifier, non-default offset/width 132s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff 133// SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00] 134// VI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00] 135