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/art/runtime/arch/arm64/
Dmemcmp16_arm64.S28 #define src1 x0 macro
53 eor tmp1, src1, src2
56 ands tmp1, src1, #7
62 ldr data1, [src1], #8
109 bic src1, src1, #7
113 ldr data1, [src1], #8
134 ldrh data1w, [src1], #2