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Searched refs:BIT28 (Results 1 – 25 of 30) sorted by relevance

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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
DPchRegsLpss.h62 #define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA
147 #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
234 #define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA
321 #define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA
413 #define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA
DPchRegsPcu.h584 #define B_PCH_SMI_STS_PUNIT_SMI BIT28 // PUNIT SMI Status
749 #define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 BIT28 // LPSS2 I2C #4
809 #define B_PCH_PMC_GPI_ROUT_14 (BIT29 | BIT28)
874 #define B_PCH_PMC_D3_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4
911 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dgeneral_definitions.h45 #undef BIT28
81 #define BIT28 0x10000000U macro
Dmeminit.c558 …l_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
603 … * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
604 …SET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT2… in ddrphy_init()
605 …FSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
606 …FSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
607 …FSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
608 …el_i * DDRIOCCC_CH_OFFSET)), ((0x6<<8)|BIT6|(0x4<<0)), (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
620 …CH0 + (channel_i * DDRCOMP_CH_OFFSET)), ((0x08<<24)|(0x03<<16)), ((BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
621 …FCH0 + (channel_i * DDRCOMP_CH_OFFSET)), ((0x0C<<24)|(0x03<<16)), ((BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
622 …FCH0 + (channel_i * DDRCOMP_CH_OFFSET)), ((0x0F<<24)|(0x03<<16)), ((BIT29|BIT28|BIT27|BIT26|BIT25|… in ddrphy_init()
[all …]
Dmeminit_utils.c73 msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); in set_rcvn()
472 …msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) | (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | B… in set_wcmd()
682 msk = (BIT31 | BIT30 | BIT29 | BIT28) | (BIT27 | BIT26 | BIT25 | BIT24); in set_wctl()
693 msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); in set_wctl()
/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/
DXPressRich3.h52 #define PCIE_INT_MSI BIT28
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
DCommonIncludes.h88 #define BIT28 0x10000000
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
DBoardFeatures.h81 #define B_BOARD_FEATURES_2_SATA BIT28 // 2SATA instead of 4(pre Ich8) or 4 SATA in…
175 #define B_BOARD_FEATURES_HDAUDIOLINK BIT28 // HD audio link support
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
DVirtio.h171 #define VIRTIO_F_RING_INDIRECT_DESC BIT28
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
DAhciMode.h111 #define EFI_AHCI_PORT_IS_HBDS BIT28
138 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
DOmap3530MMCHS.h134 #define CERR_EN BIT28
149 #define CERR_SIGEN BIT28
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
DOmap3530MMCHS.h134 #define CERR_EN BIT28
149 #define CERR_SIGEN BIT28
/device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/
DLcdGraphicsOutputDxe.h148 #define LCDENABLESIGNAL BIT28
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/
DLcdGraphicsOutputDxe.h148 #define LCDENABLESIGNAL BIT28
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchRegs.h74 #define BIT28 0x10000000 macro
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/EhciDxe/
DEhci.h78 #define USB_DEBUG_PORT_ENABLE BIT28
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
DIoh.h57 #define BIT28 0x10000000 macro
DIohCommonDefinitions.h98 #define BIT28 0x10000000 macro
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/
DBaseTypes.h249 #define BIT28 0x10000000 macro
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
DI2CLibPei.h39 #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
DLan9118DxeHw.h259 #define GPIO_LED1_ENABLE BIT28
/device/linaro/bootloader/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/
DCpuService.c69 ASSERT ((RegEdx & BIT28) != 0); in SmmGetProcessorLocation()
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
DVlvCommonDefinitions.h105 #define BIT28 0x10000000 macro
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DQNCCommonDefinitions.h98 #define BIT28 0x10000000 macro
/device/linaro/bootloader/edk2/MdePkg/Include/
DBase.h254 #define BIT28 0x10000000 macro

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