Searched refs:BIT4 (Results 1 – 25 of 117) sorted by relevance
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81 #define B_PCH_LPC_COMMAND_MWIE BIT4 // Memory Write and Invalidate Enable97 #define B_PCH_LPC_DEV_STS_CAP_LIST BIT4 // Capabilities List373 #define B_PCH_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 | BIT4) // INTB Mask375 #define V_PCH_ILB_DXXIR_IBR_PIRQB BIT4 // INTB Mapping to IRQ B377 #define V_PCH_ILB_DXXIR_IBR_PIRQD (BIT5 | BIT4) // INTB Mapping to IRQ D379 #define V_PCH_ILB_DXXIR_IBR_PIRQF (BIT6 | BIT4) // INTB Mapping to IRQ F381 #define V_PCH_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) // INTB Mapping to IRQ H415 #define B_PCH_ILB_RTCC_RTCB2 BIT4 // RTC Bias Resistor 2, Adds 120 Kohm430 #define B_PCH_ILB_DEF1_FOAR BIT4 // 8254 Freeze_On_AnyRead442 #define B_PCH_ILB_GNMI_NMIN BIT4 // NMI NOW[all …]
73 #define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable87 #define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List133 #define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4195 #define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled204 #define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented
50 #define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size81 #define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) // Opcode Type 2 Mask
60 #define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'81 #define B_PCH_SMBUS_FAIL BIT4 // Failed
37 #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor44 #define MSR_CB BIT4 // FDC Busy99 #define STS0_EC BIT4 // Equipment Check115 #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service w…130 #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from t…147 #define STS3_T0 BIT4 // Track 0
53 #define USBPORTSC_LSL BIT4 // Line Status Low BIT74 #define USBCMD_FGR BIT4 // Force Global Resume86 #define USBSTS_HCPE BIT4 // Host Controller Process Error92 #define USBTD_BABBLE BIT4 // Babble condition
37 #define MCH_SMRAM_D_LCK BIT444 #define MCH_ESMRAMC_SM_L1 BIT478 #define ICH9_GEN_PMCON_1_SMI_LOCK BIT4
61 #define I2C_INTR_TX_EMPTY BIT486 #define STAT_RFF BIT4 // RX FIFO is completely full121 #define I2C_INTR_TX_EMPTY BIT4
46 #define ISP1761_DC_INTERRUPT_RESUME BIT464 #define ISP1761_MODE_SFRESET BIT470 #define ISP1761_ENDPOINT_TYPE_NOEMPKT BIT4
94 #define EPHSR_16COL BIT4120 #define RPCR_LS2B BIT4146 #define CTR_RESERVED (BIT12 | BIT9 | BIT4)187 #define IST_RX_OVRN BIT4259 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
154 #define EFI_ERROR_SECTION_FLAGS_RESOURCE_NOT_ACCESSIBLE BIT4230 #define EFI_GENERIC_ERROR_PROC_FLAGS_VALID BIT4344 #define EFI_CACHE_CHECK_UNCORRECTED_VALID BIT4397 #define EFI_TLB_CHECK_UNCORRECTED_VALID BIT4448 #define EFI_BUS_CHECK_UNCORRECTED_VALID BIT4523 #define EFI_MS_CHECK_RESTARTABLE_VALID BIT4571 #define EFI_IA32_X64_ERROR_PROC_INST_IP_VALID BIT4758 #define EFI_PLATFORM_MEMORY_CARD_VALID BIT4834 #define EFI_PLATFORM_MEMORY2_CARD_VALID BIT4912 #define EFI_PCIE_ERROR_SERIAL_NO_VALID BIT4[all …]
28 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S Disable114 #define I2C_INTR_TX_EMPTY BIT4139 #define STAT_RFF BIT4 // RX FIFO is completely full178 #define I2C_INTR_TX_EMPTY BIT4
39 #define CTRL5_PICOPHY_ACAENB BIT456 #define RST0_USBOTG_BUS BIT4
22 #define XRDY_IE BIT429 #define XRDY BIT4
39 #define MODE BIT460 #define DDIR_READ BIT4114 #define BWR BIT4125 #define BWR_EN BIT4140 #define BWR_SIGEN BIT4
209 #define DRVA_MOTOR_ON BIT4232 #define MSR_CB BIT4343 #define STS0_EC BIT4389 #define STS1_OR BIT4423 #define STS2_WC BIT4443 #define STS3_T0 BIT4
72 #define I2C_INTR_TX_EMPTY BIT497 #define STAT_RFF BIT4 // RX FIFO is completely full134 #define I2C_INTR_TX_EMPTY BIT4
51 #define B_I2C_REG_CON_10BITADD_MASTER (BIT4) // 7-bit addressing (0) or 10-bit addres…53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) //…
21 #undef BIT457 #define BIT4 0x00000010U macro
65 #define RXSTATUS_RXW_TO BIT4 // Incomming frame larger t…95 #define IRQCFG_IRQ_POL BIT4 // IRQ Polarity105 #define INSTS_RSFF BIT4 // Rx Status FIFO full162 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
289 #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)333 #define B_CFG_STICKY_RW_WARM_RST BIT4387 #define B_QNC_SMBUS_START (BIT4) // Start/Stop495 #define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM509 #define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM731 #define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode…
143 #define TIS_PC_ACC_SEIZED BIT4175 #define TIS_PC_STS_DATA BIT4
67 #define HDLCD_BURST_16 BIT474 #define HDLCD_PXCLK_HIGH BIT4