Searched refs:CR1 (Results 1 – 5 of 5) sorted by relevance
69 volatile uint32_t CR1; member197 regs->CR1 &= ~SPI_CR1_BR_MASK; in stmSpiEnable()198 regs->CR1 |= SPI_CR1_BR(div); in stmSpiEnable()202 regs->CR1 &= ~SPI_CR1_CPOL; in stmSpiEnable()204 regs->CR1 |= SPI_CR1_CPOL; in stmSpiEnable()207 regs->CR1 &= ~SPI_CR1_CPHA; in stmSpiEnable()209 regs->CR1 |= SPI_CR1_CPHA; in stmSpiEnable()212 regs->CR1 &= ~SPI_CR1_DFF; in stmSpiEnable()214 regs->CR1 |= SPI_CR1_DFF; in stmSpiEnable()217 regs->CR1 &= ~SPI_CR1_LSBFIRST; in stmSpiEnable()[all …]
30 volatile uint16_t CR1; member114 block->CR1 = (block->CR1 &~ 0x1600) | wordLengthVals[data_bits] | parityVals[parity] | 0x800C; in usartOpen()129 block->CR1 |= 0x2000; in usartOpen()137 block->CR1 &=~ 0x2000; in usartClose()
57 volatile uint16_t CR1; member276 tim->CR1 = (tim->CR1 &~ 0x03E1) | 0x0010; //count down mode with no clock division, disabled in platInitialize()331 tim->CR1 &=~ 1; in TIM2_IRQHandler()381 tim->CR1 &=~ 1; in platSetTimerAlarm()390 tim->CR1 |= 1; in platSetTimerAlarm()463 tim->CR1 &=~ 1; in sleepClockTmrWake()
109 volatile uint32_t CR1; member252 pdev->cfg->regs->CR1 |= I2C_CR1_ACK; in stmI2cAckEnable()257 pdev->cfg->regs->CR1 &= ~I2C_CR1_ACK; in stmI2cAckDisable()274 while (regs->CR1 & (I2C_CR1_STOP | I2C_CR1_START)) in stmI2cStopEnable()276 regs->CR1 |= I2C_CR1_STOP; in stmI2cStopEnable()283 while (regs->CR1 & (I2C_CR1_STOP | I2C_CR1_START)) in stmI2cStartEnable()285 regs->CR1 |= I2C_CR1_START; in stmI2cStartEnable()302 pdev->cfg->regs->CR1 |= I2C_CR1_PE; in stmI2cEnable()307 pdev->cfg->regs->CR1 &= ~I2C_CR1_PE; in stmI2cDisable()
19 volatile uint32_t CR1; member464 SPI->CR1 = 0x00000040; //spi is on, configured same as bootloader would in blConfigIo()