Searched refs:CapLength (Results 1 – 6 of 6) sorted by relevance
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
D | XhciReg.c | 109 ASSERT (Xhc->CapLength != 0); in XhcReadOpReg() 115 (UINT64) (Xhc->CapLength + Offset), in XhcReadOpReg() 145 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg() 151 (UINT64) (Xhc->CapLength + Offset), in XhcWriteOpReg() 178 ASSERT (Xhc->CapLength != 0); in XhcWriteOpReg16() 184 (UINT64) (Xhc->CapLength + Offset), in XhcWriteOpReg16()
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D | Xhci.h | 222 UINT8 CapLength; ///< Capability Register Length member
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D | Xhci.c | 1822 Xhc->CapLength = XhcReadCapReg8 (Xhc, XHC_CAPLENGTH_OFFSET); in XhcCreateUsbHc() 1842 DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength)); in XhcCreateUsbHc()
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
D | XhcPeim.h | 152 UINT8 CapLength; ///< Capability Register Length member
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D | XhcPeim.c | 86 ASSERT (Xhc->CapLength != 0); in XhcPeiReadOpReg() 88 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg() 107 ASSERT (Xhc->CapLength != 0); in XhcPeiWriteOpReg() 109 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg() 1474 …XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0F… in XhcPeimEntry() 1490 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength)); in XhcPeimEntry()
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/device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/ |
D | DebugCommunicationLibUsb3Common.c | 237 UINT8 CapLength; in CalculateUsbDebugPortMmioBase() local 254 CapLength = MmioRead8 ((UINTN) Handle->XhciMmioBase); in CalculateUsbDebugPortMmioBase() 290 Handle->XhciOpRegister = Handle->XhciMmioBase + CapLength; in CalculateUsbDebugPortMmioBase()
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