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Searched refs:bl_i (Results 1 – 2 of 2) sorted by relevance

/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dmeminit.c1081 uint8_t bl_i; // byte lane counter in rcvn_cal() local
1130 for (bl_i=0; bl_i<(NUM_BYTE_LANES/bl_divisor); bl_i++) in rcvn_cal()
1132 set_rcvn(channel_i, rank_i, bl_i, ddr_rcvn[PLATFORM_ID]); in rcvn_cal()
1136 for (bl_i = 0; bl_i < (NUM_BYTE_LANES / bl_divisor); bl_i += 2) in rcvn_cal()
1138 …isbM32m(DDRPHY, (B01PTRCTL1 + ((bl_i >> 1) * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET))… in rcvn_cal()
1142 for (bl_i = 0; bl_i < (NUM_BYTE_LANES / bl_divisor); bl_i++) in rcvn_cal()
1146 delay[bl_i] = 3 * FULL_CLK; in rcvn_cal()
1148 delay[bl_i] = (4 + 1) * FULL_CLK; // 1x CLK domain timing is tCAS-4 in rcvn_cal()
1151 set_rcvn(channel_i, rank_i, bl_i, delay[bl_i]); in rcvn_cal()
1157 for (bl_i = 0; bl_i < (NUM_BYTE_LANES / bl_divisor); bl_i++) in rcvn_cal()
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Dmeminit_utils.c832 uint8_t bl_i; in clear_pointers() local
837 for (bl_i = 0; bl_i < NUM_BYTE_LANES; bl_i++) in clear_pointers()
839 …isbM32m(DDRPHY, (B01PTRCTL1 + (channel_i * DDRIODQ_CH_OFFSET) + ((bl_i >> 1) * DDRIODQ_BL_OFFSET))… in clear_pointers()
842 …isbM32m(DDRPHY, (B01PTRCTL1 + (channel_i * DDRIODQ_CH_OFFSET) + ((bl_i >> 1) * DDRIODQ_BL_OFFSET))… in clear_pointers()
893 uint8_t bl_i; // byte lane counter in find_rising_edge() local
909 for (bl_i = 0; bl_i < (NUM_BYTE_LANES / bl_divisor); bl_i++) in find_rising_edge()
914 set_rcvn(channel, rank, bl_i, delay[bl_i] + (sample_i * SAMPLE_DLY)); in find_rising_edge()
918 set_wdqs(channel, rank, bl_i, delay[bl_i] + (sample_i * SAMPLE_DLY)); in find_rising_edge()
931 for (bl_i = 0; bl_i < (NUM_BYTE_LANES / bl_divisor); bl_i++) in find_rising_edge()
937 …transition_pattern |= ((sample_result[sample_i] & (1 << bl_i)) >> bl_i) << (SAMPLE_CNT - 1 - sampl… in find_rising_edge()
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