Searched refs:pad_val (Results 1 – 3 of 3) sorted by relevance
237 PAD_VAL pad_val; in InternalGpioConfig()268 pad_val.dw = GPIORead32(mmio_padval); in InternalGpioConfig()275 pad_val.dw &= ~0x6; // Clear bits 1:2 in InternalGpioConfig()276 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal in InternalGpioConfig()283 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4; in InternalGpioConfig()288 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw)); in InternalGpioConfig()290 MmioWrite32(mmio_padval, pad_val.dw); in InternalGpioConfig()
293 PAD_VAL pad_val; in TristateLpcGpioConfig() local326 pad_val.dw = MmioRead32(mmio_padval); in TristateLpcGpioConfig()333 pad_val.dw &= ~0x6; // Clear bits 1:2 in TristateLpcGpioConfig()334 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal in TristateLpcGpioConfig()341 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4; in TristateLpcGpioConfig()346 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw)); in TristateLpcGpioConfig()348 MmioWrite32(mmio_padval, pad_val.dw); in TristateLpcGpioConfig()
292 …UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage e…