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Searched refs:DR0 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmLexer.cpp108 case '0': RegNo = X86::DR0; break; in LexTokenATT()
DX86AsmParser.cpp464 case '0': RegNo = X86::DR0; break; in ParseRegister()
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …BND3 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h251 ENTRY(DR0) \
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h337 ENTRY(DR0) \
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp207 case X86::CR0: case X86::CR8 : case X86::DR0: return 0; in getX86RegNum()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenRegisterInfo.inc52 DR0 = 33,
281 const unsigned DR0_Overlaps[] = { X86::DR0, 0 };
598 { "DR0", DR0_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
910 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7,
1465 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, false );
1626 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, false );
1787 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, false );
1953 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, true );
2114 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, true );
2275 RI->mapLLVMRegToDwarfReg(X86::DR0, -1, true );
[all …]
DX86RegisterInfo.td238 def DR0 : Register<"dr0">;
DX86GenAsmWriter.inc6883 case X86::DR0:
DX86GenAsmWriter1.inc7626 case X86::DR0:
DX86GenAsmMatcher.inc2754 case X86::DR0: OpKind = MCK_DEBUG_REG; break;
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td266 def DR0 : X86Reg<"dr0", 0>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h129 #define DR0 dr0 macro
191 #define DR0 %db0 macro
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp963 case '0': RegNo = X86::DR0; break; in ParseRegister()