Searched refs:FMAD (Results 1 – 10 of 10) sorted by relevance
/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 248 FMAD, enumerator
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 201 case ISD::FMAD: return "fmad"; in getOperationName()
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D | DAGCombiner.cpp | 7772 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFADDForFMACombine() 7789 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine() 7960 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFSUBForFMACombine() 7976 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine() 8230 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFMULForFMACombine() 8242 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMACombine()
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D | LegalizeFloatTypes.cpp | 1899 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
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D | LegalizeDAG.cpp | 3165 case ISD::FMAD: in ExpandNode()
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/external/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 2946 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS); in PerformDAGCombine() 2955 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS); in PerformDAGCombine() 2984 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS); in PerformDAGCombine() 2994 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS); in PerformDAGCombine()
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D | AMDGPUISelLowering.cpp | 260 setOperationAction(ISD::FMAD, MVT::f32, Legal); in AMDGPUTargetLowering() 1293 SDValue fr = DAG.getNode(ISD::FMAD, DL, FltVT, fqneg, fb, fa); in LowerDIVREM24()
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/external/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 872 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 431 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
D | PTXInstrInfo.td | 503 defm FMAD : PTX_FLOAT_4OP<"mad">, Requires<[SupportsFMA]>;
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