| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 224 const MCOperand &OffsetOp, in printMemoryImmediateOffset() argument
226 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset()
227 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
228 assert(isInt<SizeInBits>(OffsetOp.getImm()) && "Constant value truncated"); in printMemoryImmediateOffset()
229 OS << OffsetOp.getImm(); in printMemoryImmediateOffset()
231 OffsetOp.getExpr()->print(OS, &MAI); in printMemoryImmediateOffset()
238 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); in printMemRiOperand() local
243 printMemoryImmediateOffset<16>(MAI, OffsetOp, OS); in printMemRiOperand()
253 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); in printMemRrOperand() local
256 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
[all …]
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| /external/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 69 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); in printMemOperand() local
71 if (OffsetOp.isImm()) in printMemOperand()
72 O << formatDec(OffsetOp.getImm()); in printMemOperand()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 112 unsigned OffsetOp = MRI.createVirtualRegister(PtrRC); in eliminateFrameIndex() local
114 OffsetOp) in eliminateFrameIndex()
120 .addReg(OffsetOp); in eliminateFrameIndex()
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 201 const MCOperand &OffsetOp = MI.getOperand(OpNo + 1); in SMRDmemriEncode() local
204 assert(OffsetOp.isImm()); in SMRDmemriEncode()
207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK) in SMRDmemriEncode()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 143 const MachineOperand &OffsetOp = MI->getOperand(3); in canRemoveAddasl() local
144 if (!OffsetOp.isImm() || OffsetOp.getImm() > 3) in canRemoveAddasl()
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| D | HexagonInstrInfoV4.td | 1066 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1067 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1076 string OffsetOpStr = !cast<string>(OffsetOp);
1093 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1096 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1107 string OffsetOpStr = !cast<string>(OffsetOp);
1135 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1137 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1139 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1142 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 329 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex() local
330 int64_t NewOffset = OffsetOp->getImm() + Offset; in resolveFrameIndex()
334 OffsetOp->setImm(NewOffset); in resolveFrameIndex()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1108 ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset()); in tryIndexedLoad() local
1109 int OffsetVal = (int)OffsetOp->getZExtValue(); in tryIndexedLoad()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 4126 static MachinePointerInfo InferPointerInfo(SDValue Ptr, SDValue OffsetOp) { in InferPointerInfo() argument
4128 if (ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp)) in InferPointerInfo()
4130 if (OffsetOp.getOpcode() == ISD::UNDEF) in InferPointerInfo()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5043 SDValue OffsetOp) { in InferPointerInfo() argument
5045 if (ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp)) in InferPointerInfo()
5047 if (OffsetOp.isUndef()) in InferPointerInfo()
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