Searched refs:OpIndex (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsELFStreamer.cpp | 25 for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) { in EmitInstruction() local
26 const MCOperand &Op = Inst.getOperand(OpIndex); in EmitInstruction()
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| /external/swiftshader/third_party/LLVM/lib/MC/MCDisassembler/ |
| D | EDOperand.cpp | 29 OpIndex(opIndex), in EDOperand()
127 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex]; in evaluate()
246 return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeRegister); in isRegister()
254 return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeImmediate); in isImmediate()
262 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex]; in isMemory()
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| D | EDOperand.h | 39 unsigned int OpIndex; member
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| D | PTXInstPrinter.cpp | 61 int OpIndex; in printPredicate() local
65 OpIndex = 1; in printPredicate()
68 OpIndex = MI->getNumOperands()-1; in printPredicate()
71 int PredOp = MI->getOperand(OpIndex).getImm(); in printPredicate()
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 215 unsigned int OpIndex; in EmitALUInstr() local
216 for (OpIndex = 1; OpIndex < NumOperands; OpIndex++) { in EmitALUInstr()
218 if (MI.getOperand(OpIndex).isImm() || MI.getOperand(OpIndex).isFPImm()) { in EmitALUInstr()
221 EmitSrc(MI, OpIndex, OS); in EmitALUInstr()
225 for ( ; OpIndex < 4; OpIndex++) { in EmitALUInstr()
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| /external/llvm/utils/TableGen/ |
| D | AsmWriterEmitter.cpp | 683 int OpIndex, PrintIndex; in print() local
684 std::tie(OpIndex, PrintIndex) = getOpData(Name); in print()
687 OS << format("\\x%02X", (unsigned char)OpIndex + 1); in print()
691 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); in print()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1835 unsigned TypeIndex, OpIndex; in X86SelectDivRem() local
1849 case Instruction::SDiv: OpIndex = 0; break; in X86SelectDivRem()
1850 case Instruction::SRem: OpIndex = 1; break; in X86SelectDivRem()
1851 case Instruction::UDiv: OpIndex = 2; break; in X86SelectDivRem()
1852 case Instruction::URem: OpIndex = 3; break; in X86SelectDivRem()
1856 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem()
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| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 345 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); in getSingleInstruction() local
346 MCOperand &MCO = MI.getOperand(OpIndex); in getSingleInstruction()
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| /external/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 4824 for (unsigned OpIndex = 0; OpIndex < I->getNumOperands(); ++OpIndex) { in isSCEVExprNeverPoison() local
4825 const SCEV *Op = getSCEV(I->getOperand(OpIndex)); in isSCEVExprNeverPoison()
4830 if (OtherOpIndex != OpIndex) { in isSCEVExprNeverPoison()
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