| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1040 MCInst TmpInst; in EmitPatchedInstruction() local
1043 LowerARMMachineInstrToMCInst(MI, TmpInst, *this); in EmitPatchedInstruction()
1044 TmpInst.setOpcode(Opcode); in EmitPatchedInstruction()
1045 OutStreamer.EmitInstruction(TmpInst); in EmitPatchedInstruction()
1212 MCInst TmpInst; in EmitInstruction() local
1213 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR in EmitInstruction()
1216 populateADROperands(TmpInst, MI->getOperand(0).getReg(), in EmitInstruction()
1220 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
1226 MCInst TmpInst; in EmitInstruction() local
1227 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR in EmitInstruction()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 847 MCInst TmpInst; in ProcessInstruction() local
848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
850 TmpInst.addOperand(MCOperand::createImm( in ProcessInstruction()
852 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
853 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
854 Inst = TmpInst; in ProcessInstruction()
859 MCInst TmpInst; in ProcessInstruction() local
860 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
861 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction()
862 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 287 MCInst TmpInst; in HexagonProcessInstruction() local
289 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
290 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
291 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
293 MappedInst = TmpInst; in HexagonProcessInstruction()
306 MCInst TmpInst; in HexagonProcessInstruction() local
308 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
309 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
312 MappedInst = TmpInst; in HexagonProcessInstruction()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6832 MCInst TmpInst; in processInstruction() local
6833 TmpInst.setOpcode(Opcode); in processInstruction()
6834 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
6835 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6836 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6837 TmpInst.addOperand(MCOperand::createReg(0)); in processInstruction()
6838 TmpInst.addOperand(MCOperand::createImm(0)); in processInstruction()
6839 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
6840 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6841 Inst = TmpInst; in processInstruction()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1462 MCInst TmpInst; in makeCombineInst() local
1463 TmpInst.setOpcode(opCode); in makeCombineInst()
1464 TmpInst.addOperand(Rdd); in makeCombineInst()
1465 TmpInst.addOperand(MO1); in makeCombineInst()
1466 TmpInst.addOperand(MO2); in makeCombineInst()
1468 return TmpInst; in makeCombineInst()
1582 MCInst TmpInst; in processInstruction() local
1585 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1586 TmpInst.addOperand(Pd); in processInstruction()
1587 TmpInst.addOperand(Rt); in processInstruction()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 131 MCInst TmpInst; in emitR() local
132 TmpInst.setOpcode(Opcode); in emitR()
133 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
134 TmpInst.setLoc(IDLoc); in emitR()
135 getStreamer().EmitInstruction(TmpInst, *STI); in emitR()
140 MCInst TmpInst; in emitRX() local
141 TmpInst.setOpcode(Opcode); in emitRX()
142 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
143 TmpInst.addOperand(Op1); in emitRX()
144 TmpInst.setLoc(IDLoc); in emitRX()
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| D | MipsMCCodeEmitter.cpp | 193 MCInst TmpInst = MI; in encodeInstruction() local
204 LowerLargeShift(TmpInst); in encodeInstruction()
208 LowerDins(TmpInst); in encodeInstruction()
217 LowerCompactBranch(TmpInst); in encodeInstruction()
221 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
226 unsigned Opcode = TmpInst.getOpcode(); in encodeInstruction()
250 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
251 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
255 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); in encodeInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 479 MCInst TmpInst; in EmitInstruction() local
539 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); in EmitInstruction()
542 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
549 const MCOperand TR = TmpInst.getOperand(1); in EmitInstruction()
550 const MCOperand PICR = TmpInst.getOperand(0); in EmitInstruction()
553 TmpInst.getOperand(1) = in EmitInstruction()
555 TmpInst.getOperand(0) = TR; in EmitInstruction()
556 TmpInst.getOperand(2) = PICR; in EmitInstruction()
557 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
559 TmpInst.setOpcode(PPC::ADD4); in EmitInstruction()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 177 MCInst TmpInst; in emitCallInstruction() local
178 MCInstLowering.Lower(MI, TmpInst); in emitCallInstruction()
179 TmpInst.setOpcode(Lanai::BT); in emitCallInstruction()
180 OutStreamer->EmitInstruction(TmpInst, STI); in emitCallInstruction()
194 MCInst TmpInst; in customEmitInstruction() local
195 MCInstLowering.Lower(MI, TmpInst); in customEmitInstruction()
196 OutStreamer->EmitInstruction(TmpInst, STI); in customEmitInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1425 MCInst TmpInst; in EmitInstruction() local
1426 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in EmitInstruction()
1427 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1444 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr)); in EmitInstruction()
1447 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL)); in EmitInstruction()
1448 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1450 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1451 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
1456 MCInst TmpInst; in EmitInstruction() local
1457 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in EmitInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 296 MCInst TmpInst; in EmitInstruction() local
332 TmpInst.setOpcode(PPC::BL_Darwin); // Darwin vs SVR4 doesn't matter here. in EmitInstruction()
337 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr:: in EmitInstruction()
339 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
347 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); in EmitInstruction()
351 TmpInst.setOpcode(PPC::LD); in EmitInstruction()
363 TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp); in EmitInstruction()
364 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
373 TmpInst.setOpcode(PPC::MFCR); in EmitInstruction()
374 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); in EmitInstruction()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFAsmPrinter.cpp | 51 MCInst TmpInst; in EmitInstruction() local
52 MCInstLowering.Lower(MI, TmpInst); in EmitInstruction()
53 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 492 MCInst TmpInst; in EmitInstruction() local
493 TmpInst.setOpcode(AArch64::BR); in EmitInstruction()
494 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
495 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
501 MCInst TmpInst; in EmitInstruction() local
502 TmpInst.setOpcode(AArch64::B); in EmitInstruction()
503 TmpInst.addOperand(Dest); in EmitInstruction()
504 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
575 MCInst TmpInst; in EmitInstruction() local
576 MCInstLowering.Lower(MI, TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMCInstLower.cpp | 140 MCInst TmpInst; in EmitInstruction() local
141 MCInstLowering.lower(MI, TmpInst); in EmitInstruction()
142 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
153 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI); in EmitInstruction()
162 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups, in EmitInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 635 MCInst TmpInst; in EmitInstruction() local
644 TmpInst.setOpcode(X86::CALLpcrel32); in EmitInstruction()
647 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase, in EmitInstruction()
649 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
655 TmpInst.setOpcode(X86::POP32r); in EmitInstruction()
656 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg()); in EmitInstruction()
657 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
687 MCInst TmpInst; in EmitInstruction() local
688 TmpInst.setOpcode(X86::ADD32ri); in EmitInstruction()
689 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); in EmitInstruction()
[all …]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUMCInstLower.cpp | 78 MCInst TmpInst; in EmitInstruction() local
79 MCInstLowering.lower(MI, TmpInst); in EmitInstruction()
80 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430AsmPrinter.cpp | 159 MCInst TmpInst; in EmitInstruction() local
160 MCInstLowering.Lower(MI, TmpInst); in EmitInstruction()
161 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430AsmPrinter.cpp | 153 MCInst TmpInst; in EmitInstruction() local
154 MCInstLowering.Lower(MI, TmpInst); in EmitInstruction()
155 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 506 MCInst TmpInst; in expandSET() local
508 TmpInst.setLoc(IDLoc); in expandSET()
509 TmpInst.setOpcode(SP::SETHIi); in expandSET()
510 TmpInst.addOperand(MCRegOp); in expandSET()
511 TmpInst.addOperand(MCOperand::createExpr(Expr)); in expandSET()
512 Instructions.push_back(TmpInst); in expandSET()
527 MCInst TmpInst; in expandSET() local
533 TmpInst.setLoc(IDLoc); in expandSET()
534 TmpInst.setOpcode(SP::ORri); in expandSET()
535 TmpInst.addOperand(MCRegOp); in expandSET()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 4153 MCInst TmpInst; in processInstruction() local
4154 TmpInst.setOpcode(ARM::LDR_POST_IMM); in processInstruction()
4155 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
4156 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
4157 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
4158 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset in processInstruction()
4159 TmpInst.addOperand(MCOperand::CreateImm(4)); in processInstruction()
4160 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
4161 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
4162 Inst = TmpInst; in processInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeAsmPrinter.cpp | 194 MCInst TmpInst; in EmitInstruction() local
195 MCInstLowering.Lower(MI, TmpInst); in EmitInstruction()
196 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreAsmPrinter.cpp | 295 MCInst TmpInst; in EmitInstruction() local
296 MCInstLowering.Lower(MI, TmpInst); in EmitInstruction()
298 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 257 MCInst TmpInst; in EmitInstruction() local
258 MCInstLowering.Lower(MI, TmpInst); in EmitInstruction()
259 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 100 MCInst TmpInst; in tryDecodeInst() local
102 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { in tryDecodeInst()
103 MI = TmpInst; in tryDecodeInst()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXAsmPrinter.cpp | 284 MCInst TmpInst; in EmitInstruction() local
285 LowerPTXMachineInstrToMCInst(MI, TmpInst, *this); in EmitInstruction()
286 OutStreamer.EmitInstruction(TmpInst); in EmitInstruction()
|