buffer_load_dword (reference) in projects: external

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Searched refs:buffer_load_dword (Results 1 – 25 of 93) sorted by relevance

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/external/llvm/test/MC/AMDGPU/
D	mubuf.s	17 buffer_load_dword v1, off, s[4:7], s1 label 21 buffer_load_dword v1, off, ttmp[4:7], s1 label 25 buffer_load_dword v1, off, s[4:7], s1 offset:4 label 29 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc label 33 buffer_load_dword v1, off, s[4:7], s1 offset:4 slc label 37 buffer_load_dword v1, off, s[4:7], s1 offset:4 tfe label 41 buffer_load_dword v1, off, s[4:7], s1 glc tfe label 45 buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe label 49 buffer_load_dword v1, off, ttmp[4:7], s1 offset:4 glc slc tfe label 57 buffer_load_dword v1, v2, s[4:7], s1 offen label [all …]
/external/llvm/test/CodeGen/AMDGPU/
D	extract-vector-elt-build-vector-combine.ll	`4 ; GCN: buffer_load_dword 5 ; GCN: buffer_load_dword 6 ; GCN: buffer_load_dword 7 ; GCN: buffer_load_dword 47 ; GCN: buffer_load_dword 48 ; GCN: buffer_load_dword 49 ; GCN: buffer_load_dword 50 ; GCN: buffer_load_dword 93 ; GCN: buffer_load_dword 94 ; GCN: buffer_load_dword [all …]`
D	mad-combine.ll	18 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 19 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 20 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 53 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 54 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 55 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 56 ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 98 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 99 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… 100 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64… [all …]
D	indirect-private-64.ll	`16 ; SI-ALLOCA4: buffer_load_dword v 17 ; SI-ALLOCA4: buffer_load_dword v 43 ; SI-ALLOCA4: buffer_load_dword v 44 ; SI-ALLOCA4: buffer_load_dword v 45 ; SI-ALLOCA4: buffer_load_dword v 46 ; SI-ALLOCA4: buffer_load_dword v 72 ; SI-ALLOCA4: buffer_load_dword v 73 ; SI-ALLOCA4: buffer_load_dword v 101 ; SI-ALLOCA4: buffer_load_dword v 102 ; SI-ALLOCA4: buffer_load_dword v [all …]`
D	mad-sub.ll	`7 ; SI: buffer_load_dword [[REGA:v[0-9]+]] 8 ; SI: buffer_load_dword [[REGB:v[0-9]+]] 9 ; SI: buffer_load_dword [[REGC:v[0-9]+]] 31 ; SI: buffer_load_dword [[REGA:v[0-9]+]] 32 ; SI: buffer_load_dword [[REGB:v[0-9]+]] 33 ; SI: buffer_load_dword [[REGC:v[0-9]+]] 76 ; SI: buffer_load_dword [[REGA:v[0-9]+]] 77 ; SI: buffer_load_dword [[REGB:v[0-9]+]] 78 ; SI: buffer_load_dword [[REGC:v[0-9]+]] 101 ; SI: buffer_load_dword [[REGA:v[0-9]+]] [all …]`
D	commute_modifiers.ll	8 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 22 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 37 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 52 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 67 ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64… 68 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64… 84 ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64… 85 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64… 101 ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64… 102 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64… [all …]
D	fmuladd.ll	35 ; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 36 ; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 54 ; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 55 ; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 73 ; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 74 ; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 95 ; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 96 ; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 117 ; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… 118 ; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 ad… [all …]
D	amdgpu.private-memory.ll	`387 ; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:5 ; 445 ; SI: buffer_load_dword 446 ; SI: buffer_load_dword 447 ; SI: buffer_load_dword 448 ; SI: buffer_load_dword 449 ; SI: buffer_load_dword 450 ; SI: buffer_load_dword 451 ; SI: buffer_load_dword 452 ; SI: buffer_load_dword 453 ; SI: buffer_load_dword [all …]`
D	fmax3.ll	`7 ; SI: buffer_load_dword [[REGC:v[0-9]+]] 8 ; SI: buffer_load_dword [[REGB:v[0-9]+]] 9 ; SI: buffer_load_dword [[REGA:v[0-9]+]] 25 ; SI: buffer_load_dword [[REGB:v[0-9]+]] 26 ; SI: buffer_load_dword [[REGA:v[0-9]+]] 27 ; SI: buffer_load_dword [[REGC:v[0-9]+]]`
D	fmin3.ll	`8 ; SI: buffer_load_dword [[REGC:v[0-9]+]] 9 ; SI: buffer_load_dword [[REGB:v[0-9]+]] 10 ; SI: buffer_load_dword [[REGA:v[0-9]+]] 26 ; SI: buffer_load_dword [[REGB:v[0-9]+]] 27 ; SI: buffer_load_dword [[REGA:v[0-9]+]] 28 ; SI: buffer_load_dword [[REGC:v[0-9]+]]`
D	fmax_legacy.ll	10 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 11 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 31 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 32 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 51 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 52 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 71 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 72 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 91 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 92 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… [all …]
D	shift-i64-opts.ll	`7 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] 19 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] 31 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] 43 ; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]] 72 ; GCN: buffer_load_dword [[VAL:v[0-9]+]] 84 ; GCN-DAG: buffer_load_dword v[[HI:[0-9]+]] 95 ; GCN: buffer_load_dword [[VAL:v[0-9]+]] 125 ; GCN: buffer_load_dword [[VAL:v[0-9]+]] 137 ; GCN: buffer_load_dword [[VAL:v[0-9]+]] 149 ; GCN: buffer_load_dword [[VAL:v[0-9]+]] [all …]`
D	trunc-bitcast-vector.ll	`5 ; CHECK: buffer_load_dword v 16 ; CHECK: buffer_load_dword v 27 ; CHECK: buffer_load_dword v 39 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 50 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 73 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 84 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]`
D	madak.ll	10 ; GCN: buffer_load_dword [[VA:v[0-9]+]] 11 ; GCN: buffer_load_dword [[VB:v[0-9]+]] 33 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 34 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 35 ; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 65 ; GCN: buffer_load_dword [[VA:v[0-9]+]] 84 ; GCN: buffer_load_dword [[VA:v[0-9]+]] 85 ; GCN: buffer_load_dword [[VB:v[0-9]+]] 106 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]] 125 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]] [all …]
D	private-element-size.ll	35 ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} 36 ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} 37 ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} 38 ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} 101 ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} 102 ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} 103 ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} 104 ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} 105 ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16{{$}} 106 ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:20{{$}} [all …]
D	fmin_legacy.ll	45 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 46 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 64 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 65 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 83 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 84 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 102 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 103 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… 121 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 122 ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 off… [all …]
D	madmk.ll	12 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 13 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 31 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 32 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 33 ; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 64 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 65 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 129 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 130 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… 150 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr… [all …]
D	schedule-global-loads.ll	`10 ; SI-DAG: buffer_load_dword [[REG0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} 11 ; SI-DAG: buffer_load_dword [[REG1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 26 ; SI: buffer_load_dword 27 ; SI: buffer_load_dword`
D	ctpop.ll	27 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], 41 ; GCN: buffer_load_dword [[VAL1:v[0-9]+]], 42 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]], 62 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]], 176 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], 191 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], 206 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], 221 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], 237 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], 253 ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], {{0$}} [all …]
D	llvm.SI.load.dword.ll	`10 ; CHECK: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc 11 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc 12 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc 13 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen off… 15 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen…`
D	copy-illegal-type.ll	`5 ; SI: buffer_load_dword [[REG:v[0-9]+]] 15 ; SI: buffer_load_dword [[REG:v[0-9]+]] 27 ; SI: buffer_load_dword [[REG:v[0-9]+]] 41 ; SI: buffer_load_dword [[REG:v[0-9]+]] 57 ; SI: buffer_load_dword 74 ; SI: buffer_load_dword 93 ; SI: buffer_load_dword`
D	shift-and-i64-ubfe.ll	7 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 24 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 … 40 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 56 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 72 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 … 88 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 … 104 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 120 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 136 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{… 170 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 … [all …]
D	reduce-load-width-alignment.ll	`6 ; GCN: buffer_load_dword [[VAL:v[0-9]+]] 17 ; GCN: buffer_load_dword [[VAL:v[0-9]+]] 28 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4`
D	no-shrink-extloads.ll	`22 ; SI: buffer_load_dword v 44 ; SI: buffer_load_dword v 66 ; SI: buffer_load_dword v 88 ; SI: buffer_load_dword v 111 ; SI: buffer_load_dword v 158 ; SI: buffer_load_dword v 181 ; SI: buffer_load_dword v 206 ; SI: buffer_load_dword v`
/external/llvm/test/MC/Disassembler/AMDGPU/
D	mubuf_vi.txt	3 # VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01] 6 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0… 9 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x… 12 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x… 15 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x… 18 # VI: buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x50,0xe0,0x00,0x01,0x… 21 # VI: buffer_load_dword v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0… 24 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x50,0xe0,0x02,0x01,0x01,… 27 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x50,0xe0,0x02,0… 30 # VI: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x50,0xe0,0x… [all …]

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