Home
last modified time | relevance | path

Searched refs:createReg (Results 1 – 25 of 52) sorted by relevance

123

/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
[all …]
/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp257 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
325 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
329 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
350 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
616 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
619 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
622 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
625 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); in translateImmediate()
658 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
691 mcInst.addOperand(MCOperand::createReg(X86::x)); break; in translateRMRegister()
[all …]
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp476 Inst.addOperand(MCOperand::createReg(Table[RegNo])); in DecodeRegisterClass()
578 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegsRegisterClass()
602 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegs64RegisterClass()
620 Inst.addOperand(MCOperand::createReg(Register)); in DecodeModRegsRegisterClass()
1386 Op = MCOperand::createReg(operand); in addSubinstOperands()
1389 Op = MCOperand::createReg(operand); in addSubinstOperands()
1397 Op = MCOperand::createReg(operand); in addSubinstOperands()
1400 Op = MCOperand::createReg(operand); in addSubinstOperands()
1408 Op = MCOperand::createReg(operand); in addSubinstOperands()
1411 Op = MCOperand::createReg(operand); in addSubinstOperands()
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.cpp41 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
DThumb1InstrInfo.cpp30 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoopForMachoTarget()
31 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoopForMachoTarget()
33 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
DARMAsmPrinter.cpp1427 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1448 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1450 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1459 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1460 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); in EmitInstruction()
1480 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1482 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1639 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in EmitInstruction()
1640 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1643 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp435 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
444 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
445 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
449 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
450 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
494 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
527 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
533 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); in EmitInstruction()
534 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
541 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
[all …]
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp83 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
296 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
308 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
318 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
330 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDVAddr12Operand()
332 Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index])); in decodeBDVAddr12Operand()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1763 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1793 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
1798 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
1805 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
1806 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
1815 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
1833 Inst.addOperand(MCOperand::createReg(*I)); in addRegListOperands()
2043 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
2070 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
2133 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAddrMode2Operands()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp133 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
142 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
155 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
174 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
183 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
1018 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
1030 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
1031 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
1043 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
[all …]
DMipsNaClELFStreamer.cpp97 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
98 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
99 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
/external/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
178 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
190 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
192 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
202 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
/external/llvm/lib/Target/X86/AsmParser/
DX86Operand.h387 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
418 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
431 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
433 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
435 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
449 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
450 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
454 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addDstIdxOperands()
464 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOffsOperands()
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp159 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
182 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
194 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
209 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
220 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass()
229 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
238 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
247 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
262 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
[all …]
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp211 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
334 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
341 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
346 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
362 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
364 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
367 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
382 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIX16Operands()
393 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); in decodeCRBitMOperand()
/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp146 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { in createReg() function in __anon920606c00111::SystemZOperand
256 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDVAddrOperands()
258 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDVAddrOperands()
270 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
284 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDAddrOperands()
290 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDXAddrOperands()
292 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDXAddrOperands()
297 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDLAddrOperands()
570 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num, in parseRegister()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
416 TmpInst.addOperand(MCOperand::createReg(High)); in HexagonProcessInstruction()
417 TmpInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
505 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
517 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
530 MappedInst.addOperand(MCOperand::createReg(Low)); in HexagonProcessInstruction()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp367 return MCOperand::createReg(MO.getReg()); in LowerMachineOperand()
498 OutMI.addOperand(MCOperand::createReg(ReturnReg)); in Lower()
728 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest in LowerTlsAddr()
729 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base in LowerTlsAddr()
731 LEA.addOperand(MCOperand::createReg(0)); // index in LowerTlsAddr()
733 LEA.addOperand(MCOperand::createReg(0)); // seg in LowerTlsAddr()
736 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest in LowerTlsAddr()
737 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base in LowerTlsAddr()
739 LEA.addOperand(MCOperand::createReg(0)); // index in LowerTlsAddr()
741 LEA.addOperand(MCOperand::createReg(0)); // seg in LowerTlsAddr()
[all …]
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp272 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
301 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
322 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
343 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
364 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
385 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
397 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
418 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass()
431 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32spRegisterClass()
452 Inst.addOperand(MCOperand::createReg(Register)); in DecodeVectorRegisterClass()
[all …]
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
764 I.addOperand(MCOperand::createReg(Reg)); in EmitInstrReg()
783 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
784 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
793 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
794 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
795 I.addOperand(MCOperand::createReg(Reg3)); in EmitInstrRegRegReg()
/external/llvm/lib/Target/WebAssembly/Disassembler/
DWebAssemblyDisassembler.cpp110 MI.addOperand(MCOperand::createReg(Reg)); in getInstruction()
143 MI.addOperand(MCOperand::createReg(Reg)); in getInstruction()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp581 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
586 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
654 MI.insert(I, MCOperand::createReg(0)); in AddThumbPredicate()
656 MI.insert(I, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
664 MI.insert(I, MCOperand::createReg(0)); in AddThumbPredicate()
666 MI.insert(I, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
887 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
911 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
942 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass()
972 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp557 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
562 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
567 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
572 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
591 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
596 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
606 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
611 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
616 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); in addRegVSSRCOperands()
[all …]
/external/llvm/include/llvm/MC/
DMCInstBuilder.h33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp819 Inst.addOperand(MCOperand::createReg(getGPR32Reg())); in addGPR32AsmRegOperands()
824 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); in addGPRMM16AsmRegOperands()
829 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); in addGPRMM16AsmRegZeroOperands()
834 Inst.addOperand(MCOperand::createReg(getGPRMM16Reg())); in addGPRMM16AsmRegMovePOperands()
842 Inst.addOperand(MCOperand::createReg(getGPR64Reg())); in addGPR64AsmRegOperands()
847 Inst.addOperand(MCOperand::createReg(getAFGR64Reg())); in addAFGR64AsmRegOperands()
852 Inst.addOperand(MCOperand::createReg(getFGR64Reg())); in addFGR64AsmRegOperands()
857 Inst.addOperand(MCOperand::createReg(getFGR32Reg())); in addFGR32AsmRegOperands()
866 Inst.addOperand(MCOperand::createReg(getFGRH32Reg())); in addFGRH32AsmRegOperands()
871 Inst.addOperand(MCOperand::createReg(getFCCReg())); in addFCCAsmRegOperands()
[all …]

123