| /external/llvm/test/MC/Hexagon/ |
| D | v60-vcmp.s | 8 #CHECK: 1c84fb2a { q2 &= vcmp.gt(v27.uw{{ *}},{{ *}}v4.uw) }
9 q2&=vcmp.gt(v27.uw,v4.uw)
11 #CHECK: 1c8cf826 { q2 &= vcmp.gt(v24.uh{{ *}},{{ *}}v12.uh) }
12 q2&=vcmp.gt(v24.uh,v12.uh)
14 #CHECK: 1c80e720 { q0 &= vcmp.gt(v7.ub{{ *}},{{ *}}v0.ub) }
15 q0&=vcmp.gt(v7.ub,v0.ub)
17 #CHECK: 1c9aed1a { q2 &= vcmp.gt(v13.w{{ *}},{{ *}}v26.w) }
18 q2&=vcmp.gt(v13.w,v26.w)
20 #CHECK: 1c8de516 { q2 &= vcmp.gt(v5.h{{ *}},{{ *}}v13.h) }
21 q2&=vcmp.gt(v5.h,v13.h)
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc | 112 {{gt, r0, 122}, true, gt, "gt r0 122", "gt_r0_122"},
129 {{gt, r3, 124}, true, gt, "gt r3 124", "gt_r3_124"},
131 {{gt, r1, 201}, true, gt, "gt r1 201", "gt_r1_201"},
146 {{gt, r7, 84}, true, gt, "gt r7 84", "gt_r7_84"},
173 {{gt, r3, 154}, true, gt, "gt r3 154", "gt_r3_154"},
196 {{gt, r1, 181}, true, gt, "gt r1 181", "gt_r1_181"},
203 {{gt, r6, 133}, true, gt, "gt r6 133", "gt_r6_133"},
217 {{gt, r3, 174}, true, gt, "gt r3 174", "gt_r3_174"},
233 {{gt, r0, 84}, true, gt, "gt r0 84", "gt_r0_84"},
244 {{gt, r5, 55}, true, gt, "gt r5 55", "gt_r5_55"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-t32-in-it-block.cc | 2796 {{gt, r0, r0}, true, gt, "gt r0 r0", "gt_r0_r0"},
2797 {{gt, r0, r1}, true, gt, "gt r0 r1", "gt_r0_r1"},
2798 {{gt, r0, r2}, true, gt, "gt r0 r2", "gt_r0_r2"},
2799 {{gt, r0, r3}, true, gt, "gt r0 r3", "gt_r0_r3"},
2800 {{gt, r0, r4}, true, gt, "gt r0 r4", "gt_r0_r4"},
2801 {{gt, r0, r5}, true, gt, "gt r0 r5", "gt_r0_r5"},
2802 {{gt, r0, r6}, true, gt, "gt r0 r6", "gt_r0_r6"},
2803 {{gt, r0, r7}, true, gt, "gt r0 r7", "gt_r0_r7"},
2804 {{gt, r0, r8}, true, gt, "gt r0 r8", "gt_r0_r8"},
2805 {{gt, r0, r9}, true, gt, "gt r0 r9", "gt_r0_r9"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc | 126 {{gt, r6, r0, 1}, true, gt, "gt r6 r0 1", "gt_r6_r0_1"},
139 {{gt, r0, r3, 5}, true, gt, "gt r0 r3 5", "gt_r0_r3_5"},
155 {{gt, r1, r5, 5}, true, gt, "gt r1 r5 5", "gt_r1_r5_5"},
156 {{gt, r5, r4, 2}, true, gt, "gt r5 r4 2", "gt_r5_r4_2"},
157 {{gt, r0, r3, 6}, true, gt, "gt r0 r3 6", "gt_r0_r3_6"},
164 {{gt, r0, r7, 0}, true, gt, "gt r0 r7 0", "gt_r0_r7_0"},
180 {{gt, r1, r2, 7}, true, gt, "gt r1 r2 7", "gt_r1_r2_7"},
195 {{gt, r5, r6, 5}, true, gt, "gt r5 r6 5", "gt_r5_r6_5"},
221 {{gt, r4, r3, 6}, true, gt, "gt r4 r3 6", "gt_r4_r3_6"},
258 {{gt, r3, r1, 3}, true, gt, "gt r3 r1 3", "gt_r3_r1_3"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc | 863 {{gt, r0, r0}, true, gt, "gt r0 r0", "gt_r0_r0"},
864 {{gt, r0, r1}, true, gt, "gt r0 r1", "gt_r0_r1"},
865 {{gt, r0, r2}, true, gt, "gt r0 r2", "gt_r0_r2"},
866 {{gt, r0, r3}, true, gt, "gt r0 r3", "gt_r0_r3"},
867 {{gt, r0, r4}, true, gt, "gt r0 r4", "gt_r0_r4"},
868 {{gt, r0, r5}, true, gt, "gt r0 r5", "gt_r0_r5"},
869 {{gt, r0, r6}, true, gt, "gt r0 r6", "gt_r0_r6"},
870 {{gt, r0, r7}, true, gt, "gt r0 r7", "gt_r0_r7"},
871 {{gt, r1, r0}, true, gt, "gt r1 r0", "gt_r1_r0"},
872 {{gt, r1, r1}, true, gt, "gt r1 r1", "gt_r1_r1"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc | 863 {{gt, r0, r0, 0}, true, gt, "gt r0 r0 0", "gt_r0_r0_0"},
864 {{gt, r0, r1, 0}, true, gt, "gt r0 r1 0", "gt_r0_r1_0"},
865 {{gt, r0, r2, 0}, true, gt, "gt r0 r2 0", "gt_r0_r2_0"},
866 {{gt, r0, r3, 0}, true, gt, "gt r0 r3 0", "gt_r0_r3_0"},
867 {{gt, r0, r4, 0}, true, gt, "gt r0 r4 0", "gt_r0_r4_0"},
868 {{gt, r0, r5, 0}, true, gt, "gt r0 r5 0", "gt_r0_r5_0"},
869 {{gt, r0, r6, 0}, true, gt, "gt r0 r6 0", "gt_r0_r6_0"},
870 {{gt, r0, r7, 0}, true, gt, "gt r0 r7 0", "gt_r0_r7_0"},
871 {{gt, r1, r0, 0}, true, gt, "gt r1 r0 0", "gt_r1_r0_0"},
872 {{gt, r1, r1, 0}, true, gt, "gt r1 r1 0", "gt_r1_r1_0"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc | 106 {{gt, r3, r3, 0}, true, gt, "gt r3 r3 0", "gt_r3_r3_0"},
132 {{gt, r5, r5, 139}, true, gt, "gt r5 r5 139", "gt_r5_r5_139"},
169 {{gt, r3, r3, 109}, true, gt, "gt r3 r3 109", "gt_r3_r3_109"},
171 {{gt, r3, r3, 53}, true, gt, "gt r3 r3 53", "gt_r3_r3_53"},
189 {{gt, r2, r2, 154}, true, gt, "gt r2 r2 154", "gt_r2_r2_154"},
190 {{gt, r4, r4, 195}, true, gt, "gt r4 r4 195", "gt_r4_r4_195"},
200 {{gt, r7, r7, 194}, true, gt, "gt r7 r7 194", "gt_r7_r7_194"},
219 {{gt, r4, r4, 150}, true, gt, "gt r4 r4 150", "gt_r4_r4_150"},
225 {{gt, r0, r0, 47}, true, gt, "gt r0 r0 47", "gt_r0_r0_47"},
228 {{gt, r2, r2, 113}, true, gt, "gt r2 r2 113", "gt_r2_r2_113"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc | 98 {{gt, r3, r1, r0}, true, gt, "gt r3 r1 r0", "gt_r3_r1_r0"},
106 {{gt, r6, r4, r3}, true, gt, "gt r6 r4 r3", "gt_r6_r4_r3"},
136 {{gt, r7, r0, r0}, true, gt, "gt r7 r0 r0", "gt_r7_r0_r0"},
158 {{gt, r7, r5, r0}, true, gt, "gt r7 r5 r0", "gt_r7_r5_r0"},
161 {{gt, r0, r1, r4}, true, gt, "gt r0 r1 r4", "gt_r0_r1_r4"},
179 {{gt, r3, r0, r1}, true, gt, "gt r3 r0 r1", "gt_r3_r0_r1"},
189 {{gt, r7, r0, r6}, true, gt, "gt r7 r0 r6", "gt_r7_r0_r6"},
196 {{gt, r3, r4, r4}, true, gt, "gt r3 r4 r4", "gt_r3_r4_r4"},
210 {{gt, r1, r3, r6}, true, gt, "gt r1 r3 r6", "gt_r1_r3_r6"},
219 {{gt, r3, r6, r4}, true, gt, "gt r3 r6 r4", "gt_r3_r6_r4"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc | 105 {{{gt, r3, r3, r0}, true, gt, "gt r3 r3 r0", "gt_r3_r3_r0"},
107 {{gt, r7, r7, r1}, true, gt, "gt r7 r7 r1", "gt_r7_r7_r1"},
108 {{gt, r2, r2, r0}, true, gt, "gt r2 r2 r0", "gt_r2_r2_r0"},
110 {{gt, r0, r0, r0}, true, gt, "gt r0 r0 r0", "gt_r0_r0_r0"},
131 {{gt, r7, r7, r7}, true, gt, "gt r7 r7 r7", "gt_r7_r7_r7"},
151 {{gt, r2, r2, r7}, true, gt, "gt r2 r2 r7", "gt_r2_r2_r7"},
153 {{gt, r7, r7, r3}, true, gt, "gt r7 r7 r3", "gt_r7_r7_r3"},
157 {{gt, r3, r3, r1}, true, gt, "gt r3 r3 r1", "gt_r3_r3_r1"},
159 {{gt, r5, r5, r3}, true, gt, "gt r5 r5 r3", "gt_r5_r5_r3"},
165 {{gt, r7, r7, r5}, true, gt, "gt r7 r7 r5", "gt_r7_r7_r5"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc | 863 {{gt, r0, r0, r0}, true, gt, "gt r0 r0 r0", "gt_r0_r0_r0"},
864 {{gt, r0, r1, r0}, true, gt, "gt r0 r1 r0", "gt_r0_r1_r0"},
865 {{gt, r0, r2, r0}, true, gt, "gt r0 r2 r0", "gt_r0_r2_r0"},
866 {{gt, r0, r3, r0}, true, gt, "gt r0 r3 r0", "gt_r0_r3_r0"},
867 {{gt, r0, r4, r0}, true, gt, "gt r0 r4 r0", "gt_r0_r4_r0"},
868 {{gt, r0, r5, r0}, true, gt, "gt r0 r5 r0", "gt_r0_r5_r0"},
869 {{gt, r0, r6, r0}, true, gt, "gt r0 r6 r0", "gt_r0_r6_r0"},
870 {{gt, r0, r7, r0}, true, gt, "gt r0 r7 r0", "gt_r0_r7_r0"},
871 {{gt, r1, r0, r1}, true, gt, "gt r1 r0 r1", "gt_r1_r0_r1"},
872 {{gt, r1, r1, r1}, true, gt, "gt r1 r1 r1", "gt_r1_r1_r1"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc | 108 {{gt, r14, r14, r11}, true, gt, "gt r14 r14 r11", "gt_r14_r14_r11"},
113 {{gt, r7, r7, r12}, true, gt, "gt r7 r7 r12", "gt_r7_r7_r12"},
119 {{gt, r12, r12, r5}, true, gt, "gt r12 r12 r5", "gt_r12_r12_r5"},
122 {{gt, r8, r8, r4}, true, gt, "gt r8 r8 r4", "gt_r8_r8_r4"},
130 {{gt, r4, r4, r6}, true, gt, "gt r4 r4 r6", "gt_r4_r4_r6"},
138 {{gt, r5, r5, r2}, true, gt, "gt r5 r5 r2", "gt_r5_r5_r2"},
154 {{gt, r14, r14, r9}, true, gt, "gt r14 r14 r9", "gt_r14_r14_r9"},
165 {{gt, r0, r0, r10}, true, gt, "gt r0 r0 r10", "gt_r0_r0_r10"},
167 {{gt, r3, r3, r10}, true, gt, "gt r3 r3 r10", "gt_r3_r3_r10"},
170 {{gt, r0, r0, r1}, true, gt, "gt r0 r0 r1", "gt_r0_r0_r1"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc | 98 {{gt, r1, r1, LSL, r0}, true, gt, "gt r1 r1 LSL r0", "gt_r1_r1_LSL_r0"},
143 {{gt, r5, r5, ROR, r0}, true, gt, "gt r5 r5 ROR r0", "gt_r5_r5_ROR_r0"},
161 {{gt, r1, r1, ASR, r4}, true, gt, "gt r1 r1 ASR r4", "gt_r1_r1_ASR_r4"},
188 {{gt, r5, r5, LSL, r4}, true, gt, "gt r5 r5 LSL r4", "gt_r5_r5_LSL_r4"},
193 {{gt, r4, r4, ROR, r5}, true, gt, "gt r4 r4 ROR r5", "gt_r4_r4_ROR_r5"},
208 {{gt, r5, r5, ROR, r2}, true, gt, "gt r5 r5 ROR r2", "gt_r5_r5_ROR_r2"},
220 {{gt, r3, r3, ROR, r0}, true, gt, "gt r3 r3 ROR r0", "gt_r3_r3_ROR_r0"},
236 {{gt, r6, r6, LSL, r5}, true, gt, "gt r6 r6 LSL r5", "gt_r6_r6_LSL_r5"},
237 {{gt, r4, r4, LSL, r5}, true, gt, "gt r4 r4 LSL r5", "gt_r4_r4_LSL_r5"},
239 {{gt, r7, r7, LSR, r2}, true, gt, "gt r7 r7 LSR r2", "gt_r7_r7_LSR_r2"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc | 111 {{gt, r5, r3, LSL, 1}, true, gt, "gt r5 r3 LSL 1", "gt_r5_r3_LSL_1"},
116 {{gt, r6, r4, LSL, 23}, true, gt, "gt r6 r4 LSL 23", "gt_r6_r4_LSL_23"},
159 {{gt, r2, r6, LSL, 2}, true, gt, "gt r2 r6 LSL 2", "gt_r2_r6_LSL_2"},
169 {{gt, r3, r1, LSL, 20}, true, gt, "gt r3 r1 LSL 20", "gt_r3_r1_LSL_20"},
174 {{gt, r6, r3, LSL, 2}, true, gt, "gt r6 r3 LSL 2", "gt_r6_r3_LSL_2"},
182 {{gt, r3, r3, LSL, 17}, true, gt, "gt r3 r3 LSL 17", "gt_r3_r3_LSL_17"},
194 {{gt, r3, r2, LSL, 2}, true, gt, "gt r3 r2 LSL 2", "gt_r3_r2_LSL_2"},
238 {{gt, r5, r0, LSL, 6}, true, gt, "gt r5 r0 LSL 6", "gt_r5_r0_LSL_6"},
252 {{gt, r6, r1, LSL, 22}, true, gt, "gt r6 r1 LSL 22", "gt_r6_r1_LSL_22"},
260 {{gt, r3, r0, LSL, 1}, true, gt, "gt r3 r0 LSL 1", "gt_r3_r0_LSL_1"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc | 97 {{gt, r4, r6, LSR, 32}, true, gt, "gt r4 r6 LSR 32", "gt_r4_r6_LSR_32"},
106 {{gt, r6, r4, LSR, 13}, true, gt, "gt r6 r4 LSR 13", "gt_r6_r4_LSR_13"},
119 {{gt, r5, r1, ASR, 15}, true, gt, "gt r5 r1 ASR 15", "gt_r5_r1_ASR_15"},
125 {{gt, r7, r0, LSR, 26}, true, gt, "gt r7 r0 LSR 26", "gt_r7_r0_LSR_26"},
144 {{gt, r5, r3, ASR, 3}, true, gt, "gt r5 r3 ASR 3", "gt_r5_r3_ASR_3"},
154 {{gt, r1, r6, ASR, 19}, true, gt, "gt r1 r6 ASR 19", "gt_r1_r6_ASR_19"},
180 {{gt, r2, r6, ASR, 14}, true, gt, "gt r2 r6 ASR 14", "gt_r2_r6_ASR_14"},
193 {{gt, r5, r3, ASR, 8}, true, gt, "gt r5 r3 ASR 8", "gt_r5_r3_ASR_8"},
197 {{gt, r6, r7, ASR, 12}, true, gt, "gt r6 r7 ASR 12", "gt_r6_r7_ASR_12"},
232 {{gt, r1, r5, ASR, 16}, true, gt, "gt r1 r5 ASR 16", "gt_r1_r5_ASR_16"},
[all …]
|
| D | test-assembler-cond-rd-operand-const-a32-can-use-pc.cc | 147 {{gt, r6, 0x002ac000}, false, al, "gt r6 0x002ac000", "gt_r6_0x002ac000"},
236 {{gt, r6, 0x000ab000}, false, al, "gt r6 0x000ab000", "gt_r6_0x000ab000"},
261 {{gt, r7, 0x00000ab0}, false, al, "gt r7 0x00000ab0", "gt_r7_0x00000ab0"},
263 {{gt, r15, 0x00000000},
269 {{gt, r1, 0x002ac000}, false, al, "gt r1 0x002ac000", "gt_r1_0x002ac000"},
277 {{gt, r10, 0xb000000a},
306 {{gt, r3, 0x00ff0000}, false, al, "gt r3 0x00ff0000", "gt_r3_0x00ff0000"},
319 {{gt, r6, 0xb000000a}, false, al, "gt r6 0xb000000a", "gt_r6_0xb000000a"},
327 {{gt, r4, 0x00000ff0}, false, al, "gt r4 0x00000ff0", "gt_r4_0x00000ff0"},
334 {{gt, r8, 0xc000002a}, false, al, "gt r8 0xc000002a", "gt_r8_0xc000002a"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc | 275 {{gt, r13, r13, r0}, true, gt, "gt r13 r13 r0", "gt_r13_r13_r0"},
276 {{gt, r13, r13, r1}, true, gt, "gt r13 r13 r1", "gt_r13_r13_r1"},
277 {{gt, r13, r13, r2}, true, gt, "gt r13 r13 r2", "gt_r13_r13_r2"},
278 {{gt, r13, r13, r3}, true, gt, "gt r13 r13 r3", "gt_r13_r13_r3"},
279 {{gt, r13, r13, r4}, true, gt, "gt r13 r13 r4", "gt_r13_r13_r4"},
280 {{gt, r13, r13, r5}, true, gt, "gt r13 r13 r5", "gt_r13_r13_r5"},
281 {{gt, r13, r13, r6}, true, gt, "gt r13 r13 r6", "gt_r13_r13_r6"},
282 {{gt, r13, r13, r7}, true, gt, "gt r13 r13 r7", "gt_r13_r13_r7"},
283 {{gt, r13, r13, r8}, true, gt, "gt r13 r13 r8", "gt_r13_r13_r8"},
284 {{gt, r13, r13, r9}, true, gt, "gt r13 r13 r9", "gt_r13_r13_r9"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-const-a32.cc | 169 {{gt, r13, r11, 0x3fc00000},
194 {{gt, r8, r7, 0x000ff000},
224 {{gt, r3, r7, 0x02ac0000},
259 {{gt, r3, r1, 0xff000000},
379 {{gt, r1, r14, 0x02ac0000},
464 {{gt, r2, r9, 0x0ff00000},
529 {{gt, r7, r13, 0x00003fc0},
559 {{gt, r11, r4, 0x0ff00000},
594 {{gt, r4, r2, 0x00002ac0},
604 {{gt, r11, r10, 0x00ff0000},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-a32.cc | 100 {{gt, r8, r6}, "gt, r8, r6", "gt_r8_r6"},
103 {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
107 {{gt, r14, r0}, "gt, r14, r0", "gt_r14_r0"},
140 {{gt, r10, r9}, "gt, r10, r9", "gt_r10_r9"},
146 {{gt, r2, r8}, "gt, r2, r8", "gt_r2_r8"},
147 {{gt, r5, r7}, "gt, r5, r7", "gt_r5_r7"},
155 {{gt, r11, r14}, "gt, r11, r14", "gt_r11_r14"},
177 {{gt, r1, r6}, "gt, r1, r6", "gt_r1_r6"},
178 {{gt, r11, r10}, "gt, r11, r10", "gt_r11_r10"},
180 {{gt, r1, r7}, "gt, r1, r7", "gt_r1_r7"},
[all …]
|
| D | test-macro-assembler-cond-rd-rn-t32.cc | 100 {{gt, r8, r6}, "gt, r8, r6", "gt_r8_r6"},
103 {{gt, r12, r12}, "gt, r12, r12", "gt_r12_r12"},
107 {{gt, r14, r0}, "gt, r14, r0", "gt_r14_r0"},
140 {{gt, r10, r9}, "gt, r10, r9", "gt_r10_r9"},
146 {{gt, r2, r8}, "gt, r2, r8", "gt_r2_r8"},
147 {{gt, r5, r7}, "gt, r5, r7", "gt_r5_r7"},
155 {{gt, r11, r14}, "gt, r11, r14", "gt_r11_r14"},
177 {{gt, r1, r6}, "gt, r1, r6", "gt_r1_r6"},
178 {{gt, r11, r10}, "gt, r11, r10", "gt_r11_r10"},
180 {{gt, r1, r7}, "gt, r1, r7", "gt_r1_r7"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block.cc | 189 {{gt, r0, r0}, true, gt, "gt r0 r0", "gt_r0_r0"},
190 {{gt, r1, r1}, true, gt, "gt r1 r1", "gt_r1_r1"},
191 {{gt, r2, r2}, true, gt, "gt r2 r2", "gt_r2_r2"},
192 {{gt, r3, r3}, true, gt, "gt r3 r3", "gt_r3_r3"},
193 {{gt, r4, r4}, true, gt, "gt r4 r4", "gt_r4_r4"},
194 {{gt, r5, r5}, true, gt, "gt r5 r5", "gt_r5_r5"},
195 {{gt, r6, r6}, true, gt, "gt r6 r6", "gt_r6_r6"},
196 {{gt, r7, r7}, true, gt, "gt r7 r7", "gt_r7_r7"},
|
| D | test-macro-assembler-cond-rd-rn-pc-a32.cc | 459 {{gt, r0, r15}, "gt, r0, r15", "gt_r0_r15"},
460 {{gt, r1, r15}, "gt, r1, r15", "gt_r1_r15"},
461 {{gt, r2, r15}, "gt, r2, r15", "gt_r2_r15"},
462 {{gt, r3, r15}, "gt, r3, r15", "gt_r3_r15"},
463 {{gt, r4, r15}, "gt, r4, r15", "gt_r4_r15"},
464 {{gt, r5, r15}, "gt, r5, r15", "gt_r5_r15"},
465 {{gt, r6, r15}, "gt, r6, r15", "gt_r6_r15"},
466 {{gt, r7, r15}, "gt, r7, r15", "gt_r7_r15"},
467 {{gt, r8, r15}, "gt, r8, r15", "gt_r8_r15"},
468 {{gt, r9, r15}, "gt, r9, r15", "gt_r9_r15"},
[all …]
|
| D | test-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc | 106 {{gt, r13, 0x002ac000},
122 {{gt, r3, 0x00ab0000}, false, al, "gt r3 0x00ab0000", "gt_r3_0x00ab0000"},
161 {{gt, r11, 0x00000ab0},
299 {{gt, r13, 0xab000000},
352 {{gt, r8, 0x000ff000}, false, al, "gt r8 0x000ff000", "gt_r8_0x000ff000"},
490 {{gt, r0, 0x00000000}, false, al, "gt r0 0x00000000", "gt_r0_0x00000000"},
619 {{gt, r10, 0xfc000003},
665 {{gt, r7, 0x0003fc00}, false, al, "gt r7 0x0003fc00", "gt_r7_0x0003fc00"},
737 {{gt, r8, 0xff000000}, false, al, "gt r8 0xff000000", "gt_r8_0xff000000"},
797 {{gt, r7, 0x0000ff00}, false, al, "gt r7 0x0000ff00", "gt_r7_0x0000ff00"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block.cc | 191 {{gt, r0, r13, r0}, true, gt, "gt r0 r13 r0", "gt_r0_r13_r0"},
192 {{gt, r1, r13, r1}, true, gt, "gt r1 r13 r1", "gt_r1_r13_r1"},
193 {{gt, r2, r13, r2}, true, gt, "gt r2 r13 r2", "gt_r2_r13_r2"},
194 {{gt, r3, r13, r3}, true, gt, "gt r3 r13 r3", "gt_r3_r13_r3"},
195 {{gt, r4, r13, r4}, true, gt, "gt r4 r13 r4", "gt_r4_r13_r4"},
196 {{gt, r5, r13, r5}, true, gt, "gt r5 r13 r5", "gt_r5_r13_r5"},
197 {{gt, r6, r13, r6}, true, gt, "gt r6 r13 r6", "gt_r6_r13_r6"},
198 {{gt, r7, r13, r7}, true, gt, "gt r7 r13 r7", "gt_r7_r13_r7"},
|
| /external/eigen/doc/ |
| D | ClassHierarchy.dox | 18 template argument (in this case, \c Matrix inherits from \c MatrixBase<Matrix>). This allows …
77 EigenBase<%Matrix>
78 <-- DenseCoeffsBase<%Matrix> (direct access case)
79 <-- DenseBase<%Matrix>
80 <-- MatrixBase<%Matrix>
81 <-- PlainObjectBase<%Matrix> (matrix case)
88 EigenBase<%Array>
89 <-- DenseCoeffsBase<%Array> (direct access case)
90 <-- DenseBase<%Array>
91 <-- ArrayBase<%Array>
[all …]
|
| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | j.txt | 16 # CHECK: p0 = cmp.gt(r17,#-1); if (p0.new) jump:nt
22 # CHECK: p0 = cmp.gt(r17,#-1); if (p0.new) jump:t
28 # CHECK: p0 = cmp.gt(r17,#-1); if (!p0.new) jump:nt
34 # CHECK: p0 = cmp.gt(r17,#-1); if (!p0.new) jump:t
46 # CHECK: p0 = cmp.gt(r17, #21); if (p0.new) jump:nt
48 # CHECK: p0 = cmp.gt(r17, #21); if (p0.new) jump:t
50 # CHECK: p0 = cmp.gt(r17, #21); if (!p0.new) jump:nt
52 # CHECK: p0 = cmp.gt(r17, #21); if (!p0.new) jump:t
64 # CHECK: p1 = cmp.gt(r17,#-1); if (p1.new) jump:nt
70 # CHECK: p1 = cmp.gt(r17,#-1); if (p1.new) jump:t
[all …]
|