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/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.rsq.ll4 declare float @llvm.amdgcn.rsq.f32(float) #0
5 declare double @llvm.amdgcn.rsq.f64(double) #0
10 %rsq = call float @llvm.amdgcn.rsq.f32(float %src) #0
11 store float %rsq, float addrspace(1)* %out, align 4
19 %rsq = call float @llvm.amdgcn.rsq.f32(float 4.0) #0
20 store float %rsq, float addrspace(1)* %out, align 4
27 %rsq = call float @llvm.amdgcn.rsq.f32(float 100.0) #0
28 store float %rsq, float addrspace(1)* %out, align 4
35 %rsq = call double @llvm.amdgcn.rsq.f64(double %src) #0
36 store double %rsq, double addrspace(1)* %out, align 4
[all …]
Dllvm.amdgcn.rsq.legacy.ll3 declare float @llvm.amdgcn.rsq.legacy(float) #0
8 %rsq = call float @llvm.amdgcn.rsq.legacy(float %src) #0
9 store float %rsq, float addrspace(1)* %out, align 4
17 %rsq = call float @llvm.amdgcn.rsq.legacy(float 4.0) #0
18 store float %rsq, float addrspace(1)* %out, align 4
25 %rsq = call float @llvm.amdgcn.rsq.legacy(float 100.0) #0
26 store float %rsq, float addrspace(1)* %out, align 4
33 %rsq = call float @llvm.amdgcn.rsq.legacy(float undef)
34 store float %rsq, float addrspace(1)* %out, align 4
Dllvm.AMDGPU.rsq.ll5 declare float @llvm.AMDGPU.rsq.f32(float) nounwind readnone
11 %rsq = call float @llvm.AMDGPU.rsq.f32(float %src) nounwind readnone
12 store float %rsq, float addrspace(1)* %out, align 4
21 %rsq = call float @llvm.AMDGPU.rsq.f32(float 4.0) nounwind readnone
22 store float %rsq, float addrspace(1)* %out, align 4
30 %rsq = call float @llvm.AMDGPU.rsq.f32(float 100.0) nounwind readnone
31 store float %rsq, float addrspace(1)* %out, align 4
Dvi-removed-intrinsics.ll5 declare float @llvm.amdgcn.rsq.legacy(float) #0
8 %rsq = call float @llvm.amdgcn.rsq.legacy(float %src), !dbg !4
9 store float %rsq, float addrspace(1)* %out, align 4
Dllvm.amdgcn.rsq.clamp.ll4 declare float @llvm.amdgcn.rsq.clamp.f32(float) #1
5 declare double @llvm.amdgcn.rsq.clamp.f64(double) #1
18 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src)
35 %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
43 %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef)
Dllvm.AMDGPU.rsq.clamped.ll5 ; FIXME: Uses of this should be moved to llvm.amdgcn.rsq.clamped, and
8 declare float @llvm.AMDGPU.rsq.clamped.f32(float) nounwind readnone
22 %rsq_clamped = call float @llvm.AMDGPU.rsq.clamped.f32(float %src) nounwind readnone
Dllvm.AMDGPU.rsq.clamped.f64.ll4 declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
18 %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
Dpv.ll106 %98 = call float @llvm.AMDGPU.rsq.clamped.f32(float %97)
228 declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1
Dload-input-fold.ll104 declare float @llvm.AMDGPU.rsq(float) #1
Dsi-sgpr-spill.ll224 %tmp200 = call float @llvm.amdgcn.rsq.f32(float %tmp199)
408 %tmp357 = call float @llvm.amdgcn.rsq.f32(float %tmp356)
539 %tmp485 = call float @llvm.amdgcn.rsq.f32(float %tmp484)
568 %tmp514 = call float @llvm.amdgcn.rsq.f32(float %tmp513)
872 %tmp214 = call float @llvm.amdgcn.rsq.f32(float %tmp213)
1126 %tmp430 = call float @llvm.amdgcn.rsq.f32(float %tmp429)
1151 %tmp454 = call float @llvm.amdgcn.rsq.f32(float %tmp453)
1263 %tmp555 = call float @llvm.amdgcn.rsq.f32(float %tmp554)
1594 declare float @llvm.amdgcn.rsq.f32(float) #2
Dbig_alu.ll102 %tmp91 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp90)
353 %tmp332 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp331)
386 %tmp365 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp364)
412 %tmp391 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp390)
1153 %tmp878 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp877)
1295 declare float @llvm.AMDGPU.rsq.clamped.f32(float) #0
Dsgpr-copy.ll79 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56)
211 declare float @llvm.amdgcn.rsq.f32(float) #1
/external/fec/
Dsim.c10 double fac,rsq,v1,v2; in normal_rand() local
25 rsq = v1*v1 + v2*v2; in normal_rand()
26 } while(rsq >= 1.0 || rsq == 0.0); in normal_rand()
27 fac = sqrt(-2.0*log(rsq)/rsq); in normal_rand()
/external/mesa3d/src/glsl/builtins/ir/
Dinversesqrt.ir5 ((return (expression float rsq (var_ref arg0)))))
10 ((return (expression vec2 rsq (var_ref arg0)))))
15 ((return (expression vec3 rsq (var_ref arg0)))))
20 ((return (expression vec4 rsq (var_ref arg0)))))
Dnormalize.ir10 …((return (expression vec2 * (var_ref arg0) (expression float rsq (expression float dot (var_ref ar…
15 …((return (expression vec3 * (var_ref arg0) (expression float rsq (expression float dot (var_ref ar…
20 …((return (expression vec4 * (var_ref arg0) (expression float rsq (expression float dot (var_ref ar…
Datan.ir9 (expression float rsq
24 (expression vec2 rsq
39 (expression vec3 rsq
54 (expression vec4 rsq
/external/mesa3d/src/gallium/state_trackers/d3d1x/progs/d3d11gears/
Dd3d11gears.hlsl.ps.h56 rsq r0.x, r0.x
58 rsq r0.y, r0.y
62 rsq r0.x, r0.x
65 rsq r0.x, r0.x
/external/mesa3d/src/gallium/state_trackers/d3d1x/progs/d3d11spikysphere/
Dd3d11spikysphere.hlsl.ps.h33 rsq r0.x, r0.x
36 rsq r0.w, r0.w
40 rsq r0.y, r0.y
Dd3d11spikysphere.hlsl.ds.h78 rsq r1.x, r1.x
107 rsq r0.x, r0.x
112 rsq r0.x, r0.x
123 rsq r0.w, r0.w
/external/clang/test/CodeGenOpenCL/
Dbuiltins-amdgcn.cl91 // CHECK: call float @llvm.amdgcn.rsq.f32
98 // CHECK: call double @llvm.amdgcn.rsq.f64
105 // CHECK: call float @llvm.amdgcn.rsq.clamp.f32
112 // CHECK: call double @llvm.amdgcn.rsq.clamp.f64
267 // CHECK: call float @llvm.amdgcn.rsq.f32
274 // CHECK: call double @llvm.amdgcn.rsq.f64
Dbuiltins-r600.cl5 // CHECK: call float @llvm.r600.rsq.f32
13 // XCHECK: call double @llvm.r600.rsq.f64
/external/swiftshader/src/Shader/
DShaderCore.cpp313 Float4 rsq; in reciprocalSquareRoot() local
317 rsq = Float4(1.0f) / Sqrt(abs); in reciprocalSquareRoot()
321 rsq = RcpSqrt_pp(abs); in reciprocalSquareRoot()
325 rsq = rsq * (Float4(3.0f) - rsq * rsq * abs) * Float4(0.5f); in reciprocalSquareRoot()
330 rsq = Min(rsq, Float4((float&)big)); in reciprocalSquareRoot()
332 return rsq; in reciprocalSquareRoot()
849 Float4 rsq = reciprocalSquareRoot(src.x, true, pp); in rsqx() local
851 dst.x = rsq; in rsqx()
852 dst.y = rsq; in rsqx()
853 dst.z = rsq; in rsqx()
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUIntrinsics.td32 // Deprecated in favor of llvm.amdgcn.rsq
/external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/defs/
Dopcodes.txt69 rsq
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_lowering_nv50.cpp963 Instruction *rsq = bld.mkOp1(OP_RSQ, TYPE_F32, in handleSQRT() local
966 i->setSrc(1, rsq->getDef(0)); in handleSQRT()

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