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Searched refs:v8f16 (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Dfp16-vector-load-store.ll53 ; Load to one lane of v8f16
72 ; Simple store of v8f16
91 ; Store from one lane of v8f16
108 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>*)
109 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>*)
110 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 …
111 declare void @llvm.aarch64.neon.st2.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>*)
112 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*)
113 declare void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <…
169 ; Load 2 x v8f16 with de-interleaving
[all …]
Dfp16-vector-nvcast.ll46 ; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
57 ; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
68 ; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
79 ; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
Darm64-aapcs.ll146 ; Check that v8f16 can be passed and returned in registers
160 ; Check that v8f16 can be passed and returned on the stack
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h109 v8f16 = 54, // 8 x f16 enumerator
251 SimpleTy == MVT::v1i128 || SimpleTy == MVT::v8f16 || in is128BitVector()
358 case v8f16: return f16; in getVectorElementType()
400 case v8f16: in getVectorNumElements()
487 case v8f16: in getSizeInBits()
646 if (NumElements == 8) return MVT::v8f16; in getVectorVT()
DValueTypes.td83 def v8f16 : ValueType<128, 54>; // 8 x f16 vector value
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2753 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2780 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2807 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2834 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2861 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2888 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2915 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2942 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2969 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2991 VT == MVT::v8f16) { in Select()
[all …]
DAArch64CallingConvention.td33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
76 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
84 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
98 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
114 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
165 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
174 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
193 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
DAArch64InstrInfo.td1388 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1444 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1597 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1757 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2070 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2180 def : Pat<(store (v8f16 FPR128:$Rt),
2278 def : Pat<(store (v8f16 FPR128:$Rt),
2372 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2426 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2797 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
[all …]
DAArch64ISelLowering.cpp99 addQRTypeForNEON(MVT::v8f16); in AArch64TargetLowering()
344 setOperationAction(ISD::FABS, MVT::v8f16, Expand); in AArch64TargetLowering()
345 setOperationAction(ISD::FADD, MVT::v8f16, Expand); in AArch64TargetLowering()
346 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); in AArch64TargetLowering()
347 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand); in AArch64TargetLowering()
348 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
349 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); in AArch64TargetLowering()
350 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand); in AArch64TargetLowering()
351 setOperationAction(ISD::FMA, MVT::v8f16, Expand); in AArch64TargetLowering()
352 setOperationAction(ISD::FMUL, MVT::v8f16, Expand); in AArch64TargetLowering()
[all …]
DAArch64InstrFormats.td4456 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4458 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4478 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4480 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4500 def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
4502 [(set (v8f16 V128:$dst),
4503 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4852 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
4854 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
4885 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
[all …]
DAArch64RegisterInfo.td404 v8f16],
410 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16],
/external/clang/test/CodeGen/
Dbuiltins-mips-msa.c13 typedef __fp16 v8f16 __attribute__ ((vector_size(16))); typedef
44 v8f16 v8f16_a = (v8f16) {0.5, 1, 2, 3, 4, 5, 6, 7}; in test()
45 v8f16 v8f16_b = (v8f16) {1.5, 2, 3, 4, 5, 6, 7, 8}; in test()
46 v8f16 v8f16_r; in test()
/external/llvm/test/CodeGen/Mips/msa/
Dbitcast.ll56 ; are no operations for v8f16 to put in the way.
230 ; are no operations for v8f16 to put in the way.
354 ; are no operations for v8f16 to put in the way.
378 ; are no operations for v8f16 to put in the way.
401 ; are no operations for v8f16 to put in the way.
403 ; are no operations for v8f16 to put in the way.
423 ; are no operations for v8f16 to put in the way.
447 ; are no operations for v8f16 to put in the way.
471 ; are no operations for v8f16 to put in the way.
495 ; are no operations for v8f16 to put in the way.
[all …]
/external/llvm/lib/IR/
DValueTypes.cpp188 case MVT::v8f16: return "v8f16"; in getEVTString()
264 case MVT::v8f16: return VectorType::get(Type::getHalfTy(Context), 8); in getTypeForEVT()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td3280 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3283 [(set QPR:$Vd, (v8i16 (OpNode (v8f16 QPR:$Vm))))]>,
4126 v8f16, v8f16, fadd, 1>,
4187 v8f16, v8f16, fmul, 1>,
4195 def VMULslhq : N3VQSL16<0b01, 0b1001, "vmul", "f16", v8f16,
4310 v8f16, fmul_su, fadd_mlx>,
4324 v8f16, v4f16, fmul, fadd>,
4540 v8f16, fmul, fsub>,
4554 v8f16, v4f16, fmul, fsub>,
4628 v8f16, fmul, fadd>,
[all …]
DARMRegisterInfo.td313 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3526 def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>;
3530 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr),
3558 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3561 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3569 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3582 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3588 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3594 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3600 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3657 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
[all …]
DMipsSEInstrInfo.cpp212 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) in storeRegToStack()
285 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) in loadRegFromStack()
DMipsRegisterInfo.td405 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
DMipsSEISelLowering.cpp91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); in MipsSETargetLowering()
309 if (Ty != MVT::v8f16) { in addMSAFloatType()
DMipsISelLowering.cpp3528 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in getRegForInlineAsmConstraint()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp114 case MVT::v8f16: return "MVT::v8f16"; in getEnumName()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp144 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
154 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand); in AMDGPUTargetLowering()
206 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
218 setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand); in AMDGPUTargetLowering()
/external/llvm/include/llvm/IR/
DIntrinsics.td216 def llvm_v8f16_ty : LLVMType<v8f16>; // 8 x half (__fp16)