1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __RADEON_DRM_H__ 20 #define __RADEON_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #endif 25 #ifndef __RADEON_SAREA_DEFINES__ 26 #define __RADEON_SAREA_DEFINES__ 27 #define RADEON_UPLOAD_CONTEXT 0x00000001 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define RADEON_UPLOAD_VERTFMT 0x00000002 30 #define RADEON_UPLOAD_LINE 0x00000004 31 #define RADEON_UPLOAD_BUMPMAP 0x00000008 32 #define RADEON_UPLOAD_MASKS 0x00000010 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define RADEON_UPLOAD_VIEWPORT 0x00000020 35 #define RADEON_UPLOAD_SETUP 0x00000040 36 #define RADEON_UPLOAD_TCL 0x00000080 37 #define RADEON_UPLOAD_MISC 0x00000100 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define RADEON_UPLOAD_TEX0 0x00000200 40 #define RADEON_UPLOAD_TEX1 0x00000400 41 #define RADEON_UPLOAD_TEX2 0x00000800 42 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 45 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 46 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 47 #define RADEON_REQUIRE_QUIESCENCE 0x00010000 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define RADEON_UPLOAD_ZBIAS 0x00020000 50 #define RADEON_UPLOAD_ALL 0x003effff 51 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 52 #define RADEON_EMIT_PP_MISC 0 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define RADEON_EMIT_PP_CNTL 1 55 #define RADEON_EMIT_RB3D_COLORPITCH 2 56 #define RADEON_EMIT_RE_LINE_PATTERN 3 57 #define RADEON_EMIT_SE_LINE_WIDTH 4 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define RADEON_EMIT_PP_LUM_MATRIX 5 60 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 61 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 62 #define RADEON_EMIT_SE_VPORT_XSCALE 8 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define RADEON_EMIT_SE_CNTL 9 65 #define RADEON_EMIT_SE_CNTL_STATUS 10 66 #define RADEON_EMIT_RE_MISC 11 67 #define RADEON_EMIT_PP_TXFILTER_0 12 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 70 #define RADEON_EMIT_PP_TXFILTER_1 14 71 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 72 #define RADEON_EMIT_PP_TXFILTER_2 16 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 75 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 76 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 77 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define R200_EMIT_PP_TXCBLEND_0 21 80 #define R200_EMIT_PP_TXCBLEND_1 22 81 #define R200_EMIT_PP_TXCBLEND_2 23 82 #define R200_EMIT_PP_TXCBLEND_3 24 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define R200_EMIT_PP_TXCBLEND_4 25 85 #define R200_EMIT_PP_TXCBLEND_5 26 86 #define R200_EMIT_PP_TXCBLEND_6 27 87 #define R200_EMIT_PP_TXCBLEND_7 28 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 90 #define R200_EMIT_TFACTOR_0 30 91 #define R200_EMIT_VTX_FMT_0 31 92 #define R200_EMIT_VAP_CTL 32 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define R200_EMIT_MATRIX_SELECT_0 33 95 #define R200_EMIT_TEX_PROC_CTL_2 34 96 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 97 #define R200_EMIT_PP_TXFILTER_0 36 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define R200_EMIT_PP_TXFILTER_1 37 100 #define R200_EMIT_PP_TXFILTER_2 38 101 #define R200_EMIT_PP_TXFILTER_3 39 102 #define R200_EMIT_PP_TXFILTER_4 40 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define R200_EMIT_PP_TXFILTER_5 41 105 #define R200_EMIT_PP_TXOFFSET_0 42 106 #define R200_EMIT_PP_TXOFFSET_1 43 107 #define R200_EMIT_PP_TXOFFSET_2 44 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define R200_EMIT_PP_TXOFFSET_3 45 110 #define R200_EMIT_PP_TXOFFSET_4 46 111 #define R200_EMIT_PP_TXOFFSET_5 47 112 #define R200_EMIT_VTE_CNTL 48 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 115 #define R200_EMIT_PP_TAM_DEBUG3 50 116 #define R200_EMIT_PP_CNTL_X 51 117 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 120 #define R200_EMIT_RE_SCISSOR_TL_0 54 121 #define R200_EMIT_RE_SCISSOR_TL_1 55 122 #define R200_EMIT_RE_SCISSOR_TL_2 56 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 125 #define R200_EMIT_SE_VTX_STATE_CNTL 58 126 #define R200_EMIT_RE_POINTSIZE 59 127 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define R200_EMIT_PP_CUBIC_FACES_0 61 130 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 131 #define R200_EMIT_PP_CUBIC_FACES_1 63 132 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define R200_EMIT_PP_CUBIC_FACES_2 65 135 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 136 #define R200_EMIT_PP_CUBIC_FACES_3 67 137 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define R200_EMIT_PP_CUBIC_FACES_4 69 140 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 141 #define R200_EMIT_PP_CUBIC_FACES_5 71 142 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define RADEON_EMIT_PP_TEX_SIZE_0 73 145 #define RADEON_EMIT_PP_TEX_SIZE_1 74 146 #define RADEON_EMIT_PP_TEX_SIZE_2 75 147 #define R200_EMIT_RB3D_BLENDCOLOR 76 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 150 #define RADEON_EMIT_PP_CUBIC_FACES_0 78 151 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 152 #define RADEON_EMIT_PP_CUBIC_FACES_1 80 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 155 #define RADEON_EMIT_PP_CUBIC_FACES_2 82 156 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 157 #define R200_EMIT_PP_TRI_PERF_CNTL 84 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define R200_EMIT_PP_AFS_0 85 160 #define R200_EMIT_PP_AFS_1 86 161 #define R200_EMIT_ATF_TFACTOR 87 162 #define R200_EMIT_PP_TXCTLALL_0 88 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define R200_EMIT_PP_TXCTLALL_1 89 165 #define R200_EMIT_PP_TXCTLALL_2 90 166 #define R200_EMIT_PP_TXCTLALL_3 91 167 #define R200_EMIT_PP_TXCTLALL_4 92 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define R200_EMIT_PP_TXCTLALL_5 93 170 #define R200_EMIT_VAP_PVS_CNTL 94 171 #define RADEON_MAX_STATE_PACKETS 95 172 #define RADEON_CMD_PACKET 1 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define RADEON_CMD_SCALARS 2 175 #define RADEON_CMD_VECTORS 3 176 #define RADEON_CMD_DMA_DISCARD 4 177 #define RADEON_CMD_PACKET3 5 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define RADEON_CMD_PACKET3_CLIP 6 180 #define RADEON_CMD_SCALARS2 7 181 #define RADEON_CMD_WAIT 8 182 #define RADEON_CMD_VECLINEAR 9 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 typedef union { 185 int i; 186 struct { 187 unsigned char cmd_type, pad0, pad1, pad2; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 } header; 190 struct { 191 unsigned char cmd_type, packet_id, pad0, pad1; 192 } packet; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 struct { 195 unsigned char cmd_type, offset, stride, count; 196 } scalars; 197 struct { 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 unsigned char cmd_type, offset, stride, count; 200 } vectors; 201 struct { 202 unsigned char cmd_type, addr_lo, addr_hi, count; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 } veclinear; 205 struct { 206 unsigned char cmd_type, buf_idx, pad0, pad1; 207 } dma; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 struct { 210 unsigned char cmd_type, flags, pad0, pad1; 211 } wait; 212 } drm_radeon_cmd_header_t; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define RADEON_WAIT_2D 0x1 215 #define RADEON_WAIT_3D 0x2 216 #define R300_CMD_PACKET3_CLEAR 0 217 #define R300_CMD_PACKET3_RAW 1 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define R300_CMD_PACKET0 1 220 #define R300_CMD_VPU 2 221 #define R300_CMD_PACKET3 3 222 #define R300_CMD_END3D 4 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define R300_CMD_CP_DELAY 5 225 #define R300_CMD_DMA_DISCARD 6 226 #define R300_CMD_WAIT 7 227 #define R300_WAIT_2D 0x1 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define R300_WAIT_3D 0x2 230 #define R300_WAIT_2D_CLEAN 0x3 231 #define R300_WAIT_3D_CLEAN 0x4 232 #define R300_NEW_WAIT_2D_3D 0x3 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define R300_NEW_WAIT_2D_2D_CLEAN 0x4 235 #define R300_NEW_WAIT_3D_3D_CLEAN 0x6 236 #define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 237 #define R300_CMD_SCRATCH 8 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define R300_CMD_R500FP 9 240 typedef union { 241 unsigned int u; 242 struct { 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 unsigned char cmd_type, pad0, pad1, pad2; 245 } header; 246 struct { 247 unsigned char cmd_type, count, reglo, reghi; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 } packet0; 250 struct { 251 unsigned char cmd_type, count, adrlo, adrhi; 252 } vpu; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 struct { 255 unsigned char cmd_type, packet, pad0, pad1; 256 } packet3; 257 struct { 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 unsigned char cmd_type, packet; 260 unsigned short count; 261 } delay; 262 struct { 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 unsigned char cmd_type, buf_idx, pad0, pad1; 265 } dma; 266 struct { 267 unsigned char cmd_type, flags, pad0, pad1; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 } wait; 270 struct { 271 unsigned char cmd_type, reg, n_bufs, flags; 272 } scratch; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 struct { 275 unsigned char cmd_type, count, adrlo, adrhi_flags; 276 } r500fp; 277 } drm_r300_cmd_header_t; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define RADEON_FRONT 0x1 280 #define RADEON_BACK 0x2 281 #define RADEON_DEPTH 0x4 282 #define RADEON_STENCIL 0x8 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define RADEON_CLEAR_FASTZ 0x80000000 285 #define RADEON_USE_HIERZ 0x40000000 286 #define RADEON_USE_COMP_ZBUF 0x20000000 287 #define R500FP_CONSTANT_TYPE (1 << 1) 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define R500FP_CONSTANT_CLAMP (1 << 2) 290 #define RADEON_POINTS 0x1 291 #define RADEON_LINES 0x2 292 #define RADEON_LINE_STRIP 0x3 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define RADEON_TRIANGLES 0x4 295 #define RADEON_TRIANGLE_FAN 0x5 296 #define RADEON_TRIANGLE_STRIP 0x6 297 #define RADEON_BUFFER_SIZE 65536 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define RADEON_INDEX_PRIM_OFFSET 20 300 #define RADEON_SCRATCH_REG_OFFSET 32 301 #define R600_SCRATCH_REG_OFFSET 256 302 #define RADEON_NR_SAREA_CLIPRECTS 12 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define RADEON_LOCAL_TEX_HEAP 0 305 #define RADEON_GART_TEX_HEAP 1 306 #define RADEON_NR_TEX_HEAPS 2 307 #define RADEON_NR_TEX_REGIONS 64 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define RADEON_LOG_TEX_GRANULARITY 16 310 #define RADEON_MAX_TEXTURE_LEVELS 12 311 #define RADEON_MAX_TEXTURE_UNITS 3 312 #define RADEON_MAX_SURFACES 8 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define RADEON_OFFSET_SHIFT 10 315 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 316 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 317 #endif 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 typedef struct { 320 unsigned int red; 321 unsigned int green; 322 unsigned int blue; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 unsigned int alpha; 325 } radeon_color_regs_t; 326 typedef struct { 327 unsigned int pp_misc; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 unsigned int pp_fog_color; 330 unsigned int re_solid_color; 331 unsigned int rb3d_blendcntl; 332 unsigned int rb3d_depthoffset; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 unsigned int rb3d_depthpitch; 335 unsigned int rb3d_zstencilcntl; 336 unsigned int pp_cntl; 337 unsigned int rb3d_cntl; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 unsigned int rb3d_coloroffset; 340 unsigned int re_width_height; 341 unsigned int rb3d_colorpitch; 342 unsigned int se_cntl; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 unsigned int se_coord_fmt; 345 unsigned int re_line_pattern; 346 unsigned int re_line_state; 347 unsigned int se_line_width; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 unsigned int pp_lum_matrix; 350 unsigned int pp_rot_matrix_0; 351 unsigned int pp_rot_matrix_1; 352 unsigned int rb3d_stencilrefmask; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 unsigned int rb3d_ropcntl; 355 unsigned int rb3d_planemask; 356 unsigned int se_vport_xscale; 357 unsigned int se_vport_xoffset; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 unsigned int se_vport_yscale; 360 unsigned int se_vport_yoffset; 361 unsigned int se_vport_zscale; 362 unsigned int se_vport_zoffset; 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 unsigned int se_cntl_status; 365 unsigned int re_top_left; 366 unsigned int re_misc; 367 } drm_radeon_context_regs_t; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 typedef struct { 370 unsigned int se_zbias_factor; 371 unsigned int se_zbias_constant; 372 } drm_radeon_context2_regs_t; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 typedef struct { 375 unsigned int pp_txfilter; 376 unsigned int pp_txformat; 377 unsigned int pp_txoffset; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 unsigned int pp_txcblend; 380 unsigned int pp_txablend; 381 unsigned int pp_tfactor; 382 unsigned int pp_border_color; 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 } drm_radeon_texture_regs_t; 385 typedef struct { 386 unsigned int start; 387 unsigned int finish; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 unsigned int prim : 8; 390 unsigned int stateidx : 8; 391 unsigned int numverts : 16; 392 unsigned int vc_format; 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 } drm_radeon_prim_t; 395 typedef struct { 396 drm_radeon_context_regs_t context; 397 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 drm_radeon_context2_regs_t context2; 400 unsigned int dirty; 401 } drm_radeon_state_t; 402 typedef struct { 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 drm_radeon_context_regs_t context_state; 405 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 406 unsigned int dirty; 407 unsigned int vertsize; 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 unsigned int vc_format; 410 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 411 unsigned int nbox; 412 unsigned int last_frame; 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 unsigned int last_dispatch; 415 unsigned int last_clear; 416 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; 417 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 int ctx_owner; 420 int pfState; 421 int pfCurrentPage; 422 int crtc2_base; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 int tiling_enabled; 425 } drm_radeon_sarea_t; 426 #define DRM_RADEON_CP_INIT 0x00 427 #define DRM_RADEON_CP_START 0x01 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 #define DRM_RADEON_CP_STOP 0x02 430 #define DRM_RADEON_CP_RESET 0x03 431 #define DRM_RADEON_CP_IDLE 0x04 432 #define DRM_RADEON_RESET 0x05 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 #define DRM_RADEON_FULLSCREEN 0x06 435 #define DRM_RADEON_SWAP 0x07 436 #define DRM_RADEON_CLEAR 0x08 437 #define DRM_RADEON_VERTEX 0x09 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 #define DRM_RADEON_INDICES 0x0A 440 #define DRM_RADEON_NOT_USED 441 #define DRM_RADEON_STIPPLE 0x0C 442 #define DRM_RADEON_INDIRECT 0x0D 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define DRM_RADEON_TEXTURE 0x0E 445 #define DRM_RADEON_VERTEX2 0x0F 446 #define DRM_RADEON_CMDBUF 0x10 447 #define DRM_RADEON_GETPARAM 0x11 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define DRM_RADEON_FLIP 0x12 450 #define DRM_RADEON_ALLOC 0x13 451 #define DRM_RADEON_FREE 0x14 452 #define DRM_RADEON_INIT_HEAP 0x15 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define DRM_RADEON_IRQ_EMIT 0x16 455 #define DRM_RADEON_IRQ_WAIT 0x17 456 #define DRM_RADEON_CP_RESUME 0x18 457 #define DRM_RADEON_SETPARAM 0x19 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 #define DRM_RADEON_SURF_ALLOC 0x1a 460 #define DRM_RADEON_SURF_FREE 0x1b 461 #define DRM_RADEON_GEM_INFO 0x1c 462 #define DRM_RADEON_GEM_CREATE 0x1d 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 #define DRM_RADEON_GEM_MMAP 0x1e 465 #define DRM_RADEON_GEM_PREAD 0x21 466 #define DRM_RADEON_GEM_PWRITE 0x22 467 #define DRM_RADEON_GEM_SET_DOMAIN 0x23 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 #define DRM_RADEON_GEM_WAIT_IDLE 0x24 470 #define DRM_RADEON_CS 0x26 471 #define DRM_RADEON_INFO 0x27 472 #define DRM_RADEON_GEM_SET_TILING 0x28 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 #define DRM_RADEON_GEM_GET_TILING 0x29 475 #define DRM_RADEON_GEM_BUSY 0x2a 476 #define DRM_RADEON_GEM_VA 0x2b 477 #define DRM_RADEON_GEM_OP 0x2c 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 #define DRM_RADEON_GEM_USERPTR 0x2d 480 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 481 #define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START) 482 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 485 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 486 #define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET) 487 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 #define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP) 490 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 491 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 492 #define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 495 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 496 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 497 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 500 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 501 #define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP) 502 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 505 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 506 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 507 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 510 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 511 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 512 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 515 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 516 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 517 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 520 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 521 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 522 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 525 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 526 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 527 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 530 #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) 531 #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) 532 typedef struct drm_radeon_init { 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 enum { 535 RADEON_INIT_CP = 0x01, 536 RADEON_CLEANUP_CP = 0x02, 537 RADEON_INIT_R200_CP = 0x03, 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 RADEON_INIT_R300_CP = 0x04, 540 RADEON_INIT_R600_CP = 0x05 541 } func; 542 unsigned long sarea_priv_offset; 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 int is_pci; 545 int cp_mode; 546 int gart_size; 547 int ring_size; 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 int usec_timeout; 550 unsigned int fb_bpp; 551 unsigned int front_offset, front_pitch; 552 unsigned int back_offset, back_pitch; 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 unsigned int depth_bpp; 555 unsigned int depth_offset, depth_pitch; 556 unsigned long fb_offset; 557 unsigned long mmio_offset; 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 unsigned long ring_offset; 560 unsigned long ring_rptr_offset; 561 unsigned long buffers_offset; 562 unsigned long gart_textures_offset; 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 } drm_radeon_init_t; 565 typedef struct drm_radeon_cp_stop { 566 int flush; 567 int idle; 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 } drm_radeon_cp_stop_t; 570 typedef struct drm_radeon_fullscreen { 571 enum { 572 RADEON_INIT_FULLSCREEN = 0x01, 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 RADEON_CLEANUP_FULLSCREEN = 0x02 575 } func; 576 } drm_radeon_fullscreen_t; 577 #define CLEAR_X1 0 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 #define CLEAR_Y1 1 580 #define CLEAR_X2 2 581 #define CLEAR_Y2 3 582 #define CLEAR_DEPTH 4 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 typedef union drm_radeon_clear_rect { 585 float f[5]; 586 unsigned int ui[5]; 587 } drm_radeon_clear_rect_t; 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 typedef struct drm_radeon_clear { 590 unsigned int flags; 591 unsigned int clear_color; 592 unsigned int clear_depth; 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 unsigned int color_mask; 595 unsigned int depth_mask; 596 drm_radeon_clear_rect_t __user * depth_boxes; 597 } drm_radeon_clear_t; 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 typedef struct drm_radeon_vertex { 600 int prim; 601 int idx; 602 int count; 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 int discard; 605 } drm_radeon_vertex_t; 606 typedef struct drm_radeon_indices { 607 int prim; 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 int idx; 610 int start; 611 int end; 612 int discard; 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 } drm_radeon_indices_t; 615 typedef struct drm_radeon_vertex2 { 616 int idx; 617 int discard; 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 int nr_states; 620 drm_radeon_state_t __user * state; 621 int nr_prims; 622 drm_radeon_prim_t __user * prim; 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 } drm_radeon_vertex2_t; 625 typedef struct drm_radeon_cmd_buffer { 626 int bufsz; 627 char __user * buf; 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 int nbox; 630 struct drm_clip_rect __user * boxes; 631 } drm_radeon_cmd_buffer_t; 632 typedef struct drm_radeon_tex_image { 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 unsigned int x, y; 635 unsigned int width, height; 636 const void __user * data; 637 } drm_radeon_tex_image_t; 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 typedef struct drm_radeon_texture { 640 unsigned int offset; 641 int pitch; 642 int format; 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 int width; 645 int height; 646 drm_radeon_tex_image_t __user * image; 647 } drm_radeon_texture_t; 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 typedef struct drm_radeon_stipple { 650 unsigned int __user * mask; 651 } drm_radeon_stipple_t; 652 typedef struct drm_radeon_indirect { 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 int idx; 655 int start; 656 int end; 657 int discard; 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 } drm_radeon_indirect_t; 660 #define RADEON_CARD_PCI 0 661 #define RADEON_CARD_AGP 1 662 #define RADEON_CARD_PCIE 2 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 665 #define RADEON_PARAM_LAST_FRAME 2 666 #define RADEON_PARAM_LAST_DISPATCH 3 667 #define RADEON_PARAM_LAST_CLEAR 4 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 #define RADEON_PARAM_IRQ_NR 5 670 #define RADEON_PARAM_GART_BASE 6 671 #define RADEON_PARAM_REGISTER_HANDLE 7 672 #define RADEON_PARAM_STATUS_HANDLE 8 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 #define RADEON_PARAM_SAREA_HANDLE 9 675 #define RADEON_PARAM_GART_TEX_HANDLE 10 676 #define RADEON_PARAM_SCRATCH_OFFSET 11 677 #define RADEON_PARAM_CARD_TYPE 12 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 #define RADEON_PARAM_VBLANK_CRTC 13 680 #define RADEON_PARAM_FB_LOCATION 14 681 #define RADEON_PARAM_NUM_GB_PIPES 15 682 #define RADEON_PARAM_DEVICE_ID 16 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 #define RADEON_PARAM_NUM_Z_PIPES 17 685 typedef struct drm_radeon_getparam { 686 int param; 687 void __user * value; 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 } drm_radeon_getparam_t; 690 #define RADEON_MEM_REGION_GART 1 691 #define RADEON_MEM_REGION_FB 2 692 typedef struct drm_radeon_mem_alloc { 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 int region; 695 int alignment; 696 int size; 697 int __user * region_offset; 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 } drm_radeon_mem_alloc_t; 700 typedef struct drm_radeon_mem_free { 701 int region; 702 int region_offset; 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 } drm_radeon_mem_free_t; 705 typedef struct drm_radeon_mem_init_heap { 706 int region; 707 int size; 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 int start; 710 } drm_radeon_mem_init_heap_t; 711 typedef struct drm_radeon_irq_emit { 712 int __user * irq_seq; 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 } drm_radeon_irq_emit_t; 715 typedef struct drm_radeon_irq_wait { 716 int irq_seq; 717 } drm_radeon_irq_wait_t; 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 typedef struct drm_radeon_setparam { 720 unsigned int param; 721 __s64 value; 722 } drm_radeon_setparam_t; 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 #define RADEON_SETPARAM_FB_LOCATION 1 725 #define RADEON_SETPARAM_SWITCH_TILING 2 726 #define RADEON_SETPARAM_PCIGART_LOCATION 3 727 #define RADEON_SETPARAM_NEW_MEMMAP 4 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 730 #define RADEON_SETPARAM_VBLANK_CRTC 6 731 typedef struct drm_radeon_surface_alloc { 732 unsigned int address; 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 unsigned int size; 735 unsigned int flags; 736 } drm_radeon_surface_alloc_t; 737 typedef struct drm_radeon_surface_free { 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 unsigned int address; 740 } drm_radeon_surface_free_t; 741 #define DRM_RADEON_VBLANK_CRTC1 1 742 #define DRM_RADEON_VBLANK_CRTC2 2 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 #define RADEON_GEM_DOMAIN_CPU 0x1 745 #define RADEON_GEM_DOMAIN_GTT 0x2 746 #define RADEON_GEM_DOMAIN_VRAM 0x4 747 struct drm_radeon_gem_info { 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 __u64 gart_size; 750 __u64 vram_size; 751 __u64 vram_visible; 752 }; 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 #define RADEON_GEM_NO_BACKING_STORE (1 << 0) 755 #define RADEON_GEM_GTT_UC (1 << 1) 756 #define RADEON_GEM_GTT_WC (1 << 2) 757 #define RADEON_GEM_CPU_ACCESS (1 << 3) 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4) 760 struct drm_radeon_gem_create { 761 __u64 size; 762 __u64 alignment; 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 __u32 handle; 765 __u32 initial_domain; 766 __u32 flags; 767 }; 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 #define RADEON_GEM_USERPTR_READONLY (1 << 0) 770 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1) 771 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2) 772 #define RADEON_GEM_USERPTR_REGISTER (1 << 3) 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 struct drm_radeon_gem_userptr { 775 __u64 addr; 776 __u64 size; 777 __u32 flags; 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 __u32 handle; 780 }; 781 #define RADEON_TILING_MACRO 0x1 782 #define RADEON_TILING_MICRO 0x2 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 #define RADEON_TILING_SWAP_16BIT 0x4 785 #define RADEON_TILING_SWAP_32BIT 0x8 786 #define RADEON_TILING_SURFACE 0x10 787 #define RADEON_TILING_MICRO_SQUARE 0x20 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 #define RADEON_TILING_EG_BANKW_SHIFT 8 790 #define RADEON_TILING_EG_BANKW_MASK 0xf 791 #define RADEON_TILING_EG_BANKH_SHIFT 12 792 #define RADEON_TILING_EG_BANKH_MASK 0xf 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 795 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 796 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 797 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 800 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 801 struct drm_radeon_gem_set_tiling { 802 __u32 handle; 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 __u32 tiling_flags; 805 __u32 pitch; 806 }; 807 struct drm_radeon_gem_get_tiling { 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 __u32 handle; 810 __u32 tiling_flags; 811 __u32 pitch; 812 }; 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 struct drm_radeon_gem_mmap { 815 __u32 handle; 816 __u32 pad; 817 __u64 offset; 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 __u64 size; 820 __u64 addr_ptr; 821 }; 822 struct drm_radeon_gem_set_domain { 823 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 __u32 handle; 825 __u32 read_domains; 826 __u32 write_domain; 827 }; 828 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 struct drm_radeon_gem_wait_idle { 830 __u32 handle; 831 __u32 pad; 832 }; 833 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834 struct drm_radeon_gem_busy { 835 __u32 handle; 836 __u32 domain; 837 }; 838 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 struct drm_radeon_gem_pread { 840 __u32 handle; 841 __u32 pad; 842 __u64 offset; 843 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 __u64 size; 845 __u64 data_ptr; 846 }; 847 struct drm_radeon_gem_pwrite { 848 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 __u32 handle; 850 __u32 pad; 851 __u64 offset; 852 __u64 size; 853 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854 __u64 data_ptr; 855 }; 856 struct drm_radeon_gem_op { 857 __u32 handle; 858 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859 __u32 op; 860 __u64 value; 861 }; 862 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 863 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 865 #define RADEON_VA_MAP 1 866 #define RADEON_VA_UNMAP 2 867 #define RADEON_VA_RESULT_OK 0 868 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 #define RADEON_VA_RESULT_ERROR 1 870 #define RADEON_VA_RESULT_VA_EXIST 2 871 #define RADEON_VM_PAGE_VALID (1 << 0) 872 #define RADEON_VM_PAGE_READABLE (1 << 1) 873 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874 #define RADEON_VM_PAGE_WRITEABLE (1 << 2) 875 #define RADEON_VM_PAGE_SYSTEM (1 << 3) 876 #define RADEON_VM_PAGE_SNOOPED (1 << 4) 877 struct drm_radeon_gem_va { 878 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 __u32 handle; 880 __u32 operation; 881 __u32 vm_id; 882 __u32 flags; 883 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 __u64 offset; 885 }; 886 #define RADEON_CHUNK_ID_RELOCS 0x01 887 #define RADEON_CHUNK_ID_IB 0x02 888 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889 #define RADEON_CHUNK_ID_FLAGS 0x03 890 #define RADEON_CHUNK_ID_CONST_IB 0x04 891 #define RADEON_CS_KEEP_TILING_FLAGS 0x01 892 #define RADEON_CS_USE_VM 0x02 893 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894 #define RADEON_CS_END_OF_FRAME 0x04 895 #define RADEON_CS_RING_GFX 0 896 #define RADEON_CS_RING_COMPUTE 1 897 #define RADEON_CS_RING_DMA 2 898 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899 #define RADEON_CS_RING_UVD 3 900 #define RADEON_CS_RING_VCE 4 901 struct drm_radeon_cs_chunk { 902 __u32 chunk_id; 903 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904 __u32 length_dw; 905 __u64 chunk_data; 906 }; 907 #define RADEON_RELOC_PRIO_MASK (0xf << 0) 908 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909 struct drm_radeon_cs_reloc { 910 __u32 handle; 911 __u32 read_domains; 912 __u32 write_domain; 913 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914 __u32 flags; 915 }; 916 struct drm_radeon_cs { 917 __u32 num_chunks; 918 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919 __u32 cs_id; 920 __u64 chunks; 921 __u64 gart_limit; 922 __u64 vram_limit; 923 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924 }; 925 #define RADEON_INFO_DEVICE_ID 0x00 926 #define RADEON_INFO_NUM_GB_PIPES 0x01 927 #define RADEON_INFO_NUM_Z_PIPES 0x02 928 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929 #define RADEON_INFO_ACCEL_WORKING 0x03 930 #define RADEON_INFO_CRTC_FROM_ID 0x04 931 #define RADEON_INFO_ACCEL_WORKING2 0x05 932 #define RADEON_INFO_TILING_CONFIG 0x06 933 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934 #define RADEON_INFO_WANT_HYPERZ 0x07 935 #define RADEON_INFO_WANT_CMASK 0x08 936 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 937 #define RADEON_INFO_NUM_BACKENDS 0x0a 938 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939 #define RADEON_INFO_NUM_TILE_PIPES 0x0b 940 #define RADEON_INFO_FUSION_GART_WORKING 0x0c 941 #define RADEON_INFO_BACKEND_MAP 0x0d 942 #define RADEON_INFO_VA_START 0x0e 943 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 945 #define RADEON_INFO_MAX_PIPES 0x10 946 #define RADEON_INFO_TIMESTAMP 0x11 947 #define RADEON_INFO_MAX_SE 0x12 948 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949 #define RADEON_INFO_MAX_SH_PER_SE 0x13 950 #define RADEON_INFO_FASTFB_WORKING 0x14 951 #define RADEON_INFO_RING_WORKING 0x15 952 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 953 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 955 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 956 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 957 #define RADEON_INFO_MAX_SCLK 0x1a 958 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959 #define RADEON_INFO_VCE_FW_VERSION 0x1b 960 #define RADEON_INFO_VCE_FB_VERSION 0x1c 961 #define RADEON_INFO_NUM_BYTES_MOVED 0x1d 962 #define RADEON_INFO_VRAM_USAGE 0x1e 963 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964 #define RADEON_INFO_GTT_USAGE 0x1f 965 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20 966 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21 967 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22 968 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23 970 #define RADEON_INFO_READ_REG 0x24 971 #define RADEON_INFO_VA_UNMAP_WORKING 0x25 972 #define RADEON_INFO_GPU_RESET_COUNTER 0x26 973 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974 struct drm_radeon_info { 975 __u32 request; 976 __u32 pad; 977 __u64 value; 978 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979 }; 980 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 981 #define SI_TILE_MODE_COLOR_1D 13 982 #define SI_TILE_MODE_COLOR_1D_SCANOUT 9 983 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984 #define SI_TILE_MODE_COLOR_2D_8BPP 14 985 #define SI_TILE_MODE_COLOR_2D_16BPP 15 986 #define SI_TILE_MODE_COLOR_2D_32BPP 16 987 #define SI_TILE_MODE_COLOR_2D_64BPP 17 988 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 990 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 991 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4 992 #define SI_TILE_MODE_DEPTH_STENCIL_2D 0 993 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 995 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 996 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 997 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 998 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999 #ifdef __cplusplus 1000 #endif 1001 #endif 1002