1 /** @file
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
4
5
6 This program and the accompanying materials are licensed and made available under
7
8 the terms and conditions of the BSD License that accompanies this distribution.
9
10 The full text of the license may be found at
11
12 http://opensource.org/licenses/bsd-license.php.
13
14
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20
21
22
23
24 Module Name:
25
26 PlatformEarlyInit.c
27
28 Abstract:
29
30 Do platform specific PEI stage initializations.
31
32 --*/
33
34
35 #include "PlatformEarlyInit.h"
36
37 #ifdef __GNUC__
38 #pragma GCC push_options
39 #pragma GCC optimize ("O0")
40 #else
41 #pragma optimize ("", off)
42 #endif
43
44
45
46 static EFI_PEI_STALL_PPI mStallPpi = {
47 PEI_STALL_RESOLUTION,
48 Stall
49 };
50
51 static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {
52 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
53 &gEfiPeiStallPpiGuid,
54 &mStallPpi
55 };
56
57 //
58 // The reserved SMBus addresses are defined in PlatformDxe.h file.
59 //
60 static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
61 static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {
62 SMBUS_BASE_ADDRESS,
63 SMBUS_BUS_DEV_FUNC,
64 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,
65 mSmbusRsvdAddresses
66 };
67
68 static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {
69 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
70 &gPeiSmbusPolicyPpiGuid,
71 &mSmbusPolicyPpi
72 };
73 static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {
74 ProgramToneFrequency,
75 GenerateBeepTone
76 };
77
78 static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {
79 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
80 &gPeiSpeakerInterfacePpiGuid,
81 &mSpeakerInterfacePpi
82 };
83
84 static EFI_PEI_RESET_PPI mResetPpi = { IchReset };
85
86
87 static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {
88 (EFI_PEI_FIND_FV_FINDFV)FindFv
89 };
90
91 static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
92 {
93 EFI_PEI_PPI_DESCRIPTOR_PPI,
94 &gEfiPeiMasterBootModePpiGuid,
95 NULL
96 },
97 {
98 EFI_PEI_PPI_DESCRIPTOR_PPI,
99 &gEfiPeiResetPpiGuid,
100 &mResetPpi
101 },
102 {
103 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
104 &gEfiFindFvPpiGuid,
105 &mEfiFindFvPpi
106 }
107 };
108
109 static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
110 {
111 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
112 &gEfiEndOfPeiSignalPpiGuid,
113 (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback
114 },
115 {
116 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
117 &gEfiPeiMemoryDiscoveredPpiGuid,
118 (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback
119 }
120
121 };
122
123
124 /**
125
126 Parse the status registers for figuring out the wake-up event and save it into
127 an GUID HOB which will be referenced later. However, modification is required
128 to meet the chipset register definition and the practical hardware design. Thus,
129 this is just an example.
130
131
GetWakeupEventAndSaveToHob(IN CONST EFI_PEI_SERVICES ** PeiServices)132 @param PeiServices pointer to the PEI Service Table
133 @param EFI_SUCCESS Always return Success
134
135 @retval None
136
137
138 **/
139 EFI_STATUS
140 EFIAPI
141 GetWakeupEventAndSaveToHob (
142 IN CONST EFI_PEI_SERVICES **PeiServices
143 )
144 {
145 UINT16 Pm1Sts;
146 UINTN Gpe0Sts;
147 UINTN WakeEventData;
148
149 //
150 // Read the ACPI registers
151 //
152 Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
153 Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
154
155 //
156 // Figure out the wake-up event
157 //
158 if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {
159 WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
160 } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {
161 WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;
162 } else if (Gpe0Sts != 0) {
163 WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;
164 } else {
165 WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;
166 }
167
168 DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));
169
170 return EFI_SUCCESS;
171 }
172
173 EFI_STATUS
174 GetSetupVariable (
175 IN CONST EFI_PEI_SERVICES **PeiServices,
176 IN SYSTEM_CONFIGURATION *SystemConfiguration
177 )
178 {
179 UINTN VariableSize;
180 EFI_STATUS Status;
181 EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
182
183 VariableSize = sizeof (SYSTEM_CONFIGURATION);
184 ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
185
186 Status = (*PeiServices)->LocatePpi (
187 PeiServices,
188 &gEfiPeiReadOnlyVariable2PpiGuid,
189 0,
190 NULL,
191 (void **)&Variable
192 );
193 ASSERT_EFI_ERROR (Status);
194
195 //
196 // Use normal setup default from NVRAM variable,
197 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
198 //
199 VariableSize = sizeof(SYSTEM_CONFIGURATION);
200 Status = Variable->GetVariable (
201 Variable,
202 L"Setup",
203 &gEfiSetupVariableGuid,
204 NULL,
205 &VariableSize,
206 SystemConfiguration
207 );
208 if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
209 //The setup variable is corrupted
210 VariableSize = sizeof(SYSTEM_CONFIGURATION);
211 Status = Variable->GetVariable(
212 Variable,
213 L"SetupRecovery",
214 &gEfiSetupVariableGuid,
215 NULL,
VlvPolicyInit(IN CONST EFI_PEI_SERVICES ** PeiServices,IN SYSTEM_CONFIGURATION * SystemConfiguration)216 &VariableSize,
217 SystemConfiguration
218 );
219 ASSERT_EFI_ERROR (Status);
220 }
221 return Status;
222 }
223
224 EFI_STATUS
225 VlvPolicyInit (
226 IN CONST EFI_PEI_SERVICES **PeiServices,
227 IN SYSTEM_CONFIGURATION *SystemConfiguration
228 )
229 {
230 EFI_STATUS Status;
231 EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;
232 VLV_POLICY_PPI *mVlvPolicyPpi;
233
234 Status = (*PeiServices)->AllocatePool(
235 PeiServices,
236 sizeof (EFI_PEI_PPI_DESCRIPTOR),
237 (void **)&mVlvPolicyPpiDesc
238 );
239 ASSERT_EFI_ERROR (Status);
240
241 Status = (*PeiServices)->AllocatePool(
242 PeiServices,
243 sizeof (VLV_POLICY_PPI),
244 (void **)&mVlvPolicyPpi
245 );
246 ASSERT_EFI_ERROR (Status);
247
248 //
249 // Initialize PPI
250 //
251 (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);
252 mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
253 mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;
254 mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;
255 mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;
256 mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;
257 mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;
258 mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;
259 if (SystemConfiguration->PrimaryVideoAdaptor != 2) {
260 mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;
261 } else {
262 mVlvPolicyPpi->GtConfig.InternalGraphics = 0;
263 }
264
265
266 mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;
267
268
269 mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;
270 mVlvPolicyPpi->PlatformData.DynSR = 1;
271 DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));
272 mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;
273 DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));
274 mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;
275 if (SystemConfiguration->ISPEn == 0) {
276 mVlvPolicyPpi->ISPPciDevConfig = 0;
277 DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));
278 }
279 Status = (*PeiServices)->InstallPpi(
280 PeiServices,
ConfigureSoCGpio(IN SYSTEM_CONFIGURATION * SystemConfiguration)281 mVlvPolicyPpiDesc
282 );
283 ASSERT_EFI_ERROR (Status);
284
285 return EFI_SUCCESS;
286 }
287
288
289 EFI_STATUS
290 ConfigureSoCGpio (
291 IN SYSTEM_CONFIGURATION *SystemConfiguration
292 )
293 {
294
295 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));
296 if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode
297 DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));
298
299 //
300 //Silicon Steppings
301 //
302 switch (PchStepping()) {
303 case PchA0: // SOC A0 and A1
304 case PchA1:
305 DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
306 SystemConfiguration->LpsseMMCEnabled = 1;
307 SystemConfiguration->LpsseMMC45Enabled = 0;
308 break;
309 case PchB0: // SOC B0 and later
310 default:
311 DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
312 SystemConfiguration->LpsseMMCEnabled = 0;
313 SystemConfiguration->LpsseMMC45Enabled = 1;
314 break;
315 }
316 } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41
317 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));
318 SystemConfiguration->LpsseMMCEnabled = 1;
319 SystemConfiguration->LpsseMMC45Enabled = 0;
320 } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5
321 DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));
322 SystemConfiguration->LpsseMMCEnabled = 0;
323 SystemConfiguration->LpsseMMC45Enabled = 1;
324
325 } else { // Disable eMMC controllers
326 DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));
327 SystemConfiguration->LpsseMMCEnabled = 0;
328 SystemConfiguration->LpsseMMC45Enabled = 0;
329 }
330
331 /*
332 20.1.1 EMMC
333 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
334 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
335 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
336 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
337 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
338 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
339 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
340 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
341 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
342 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
343 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
344 */
345 if (SystemConfiguration->LpsseMMCEnabled== 1) {
346 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
347 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
348 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
349 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
350 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
351 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
352 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
353 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
354 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
355 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
356 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);
357 }
358
359 /*
360 eMMC 4.5 controller
361 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
362 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
363 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
364 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
365 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
366 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
367 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
368 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
369 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
370 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
371 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
372 */
373 if (SystemConfiguration->LpsseMMC45Enabled== 1) {
374 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5
375 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);
376 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);
377 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);
378 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);
379 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);
380 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);
381 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);
382 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);
383 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);
384 MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);
385
386 }
387
388 //
MeasuredBootInit(IN CONST EFI_PEI_SERVICES ** PeiServices,IN SYSTEM_CONFIGURATION * SystemConfiguration)389 // Change GPIOC_0 setting to allow MMIO access under Android.
390 //
391 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
392 (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));
393 DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));
394 return EFI_SUCCESS;
395 }
396
397 EFI_STATUS
398 MeasuredBootInit (
399 IN CONST EFI_PEI_SERVICES **PeiServices,
400 IN SYSTEM_CONFIGURATION *SystemConfiguration
401 )
402 {
403 if (SystemConfiguration->MeasuredBootEnable) {
404 PcdSetBool (PcdMeasuredBootEnable, TRUE);
ConfigureLpssAndSccGpio(IN SYSTEM_CONFIGURATION * SystemConfiguration,IN EFI_PLATFORM_INFO_HOB * PlatformInfo)405 } else {
406 PcdSetBool (PcdMeasuredBootEnable, FALSE);
407 }
408
409 return EFI_SUCCESS;
410 }
411
412
413 EFI_STATUS
414 ConfigureLpssAndSccGpio (
415 IN SYSTEM_CONFIGURATION *SystemConfiguration,
416 IN EFI_PLATFORM_INFO_HOB *PlatformInfo
417 )
418 {
419 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
420 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
421 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
422 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
423 */
424 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));
425
426 /*
427 19.1.1 PWM0
428 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
429 19.1.2 PWM1
430 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
431 */
432 if (SystemConfiguration->LpssPwm0Enabled== 1) {
433 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);
434 } else if (SystemConfiguration->LpssPwm0Enabled== 0) {
435 MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);
436 }
437
438 if (SystemConfiguration->LpssPwm1Enabled== 1) {
439 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);
440 } else if (SystemConfiguration->LpssPwm1Enabled== 0) {
441 MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);
442 }
443
444 /*
445 19.1.3 UART1
446 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
447 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
448 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
449 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
450 */
451 if (SystemConfiguration->LpssHsuart0Enabled== 1) {
452 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1
453 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);
454 if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {
455 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));
456 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);
457 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);
458 } else {
459 DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));
460 MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);
461 MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
462 }
463 } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {
464 MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1
465 MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);
466 }
467
468
469 /*
470 19.1.4 UART2
471 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
472 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
473 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
474 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
475 */
476 if (SystemConfiguration->LpssHsuart1Enabled== 1) {
477 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);
478 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);
479
480 if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {
481 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));
482 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B
483 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B
484 } else {
485 DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));
486 MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2
487 MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
488 }
489 } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {
490 MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);
491 MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);
492 }
493
494 /*
495 19.1.5 SPI
496 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
497 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
498 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
499 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
500 */
501 if (SystemConfiguration->LpssSpiEnabled== 1) {
502 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI
503 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);
504 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);
505 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);
506 } else if (SystemConfiguration->LpssSpiEnabled== 0) {
507 MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);
508 MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);
509 MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);
510 MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);
511 }
512
513 /*
514 19.1.6 I2C0
515 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
516 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
517 */
518 if (SystemConfiguration->LpssI2C0Enabled== 1) {
519 MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);
520 MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);
521 }
522 /*
523 19.1.7 I2C1
524 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
525 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
526 */
527
528 if (SystemConfiguration->LpssI2C1Enabled== 1) {
529 MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);
530 MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);
531 }
532 /*
533 19.1.8 I2C2
534 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
535 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
536 */
537 if (SystemConfiguration->LpssI2C2Enabled== 1) {
538 MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);
539 MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);
540 }
541 /*
542 19.1.9 I2C3
543 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
544 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
545 */
546 if (SystemConfiguration->LpssI2C3Enabled== 1) {
547 MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);
548 MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);
549 }
550 /*
551 19.1.10 I2C4
552 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
553 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
554 */
555 if (SystemConfiguration->LpssI2C4Enabled== 1) {
556 MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);
557 MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);
558 }
559 /*
560 19.1.11 I2C5
561 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
562 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
563 */
564 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
565 if (SystemConfiguration->LpssI2C5Enabled== 1) {
566 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);
567 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);
568 } else if(SystemConfiguration->LpssI2C5Enabled== 0) {
569 MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);
570 MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);
571 }
572 /*
573 19.1.12 I2C6
574 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
575 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
576 */
577 if (SystemConfiguration->LpssI2C6Enabled== 1) {
578 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);
579 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);
580 } else if (SystemConfiguration->LpssI2C6Enabled== 0) {
581 MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);
582 MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);
583 }
584
585
586 /*
587 20.1.2 SDIO
588 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
589 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
590 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
591 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
592 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
593 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
594 */
595 if (SystemConfiguration->LpssSdioEnabled== 1) {
596 MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO
597 MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);
598 MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);
599 MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);
600 MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);
601 MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);
602 }
603
604 /*
605 20.1.3 SD Card
606 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
607 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
608 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
609 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
610 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
611 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
612 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
613 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
614 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
615 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
616 */
617 if (SystemConfiguration->LpssSdcardEnabled == 1) {
618 if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {
619 MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD
620 MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);
621 MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);
622 MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);
623 MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);
624 MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);
625 MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);
626 MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);
627 MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
ConfigureLpeGpio(IN SYSTEM_CONFIGURATION * SystemConfiguration)628 }
629 }
630
631
632 DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));
633 return EFI_SUCCESS;
634 }
635
636 EFI_STATUS
637 ConfigureLpeGpio (
638 IN SYSTEM_CONFIGURATION *SystemConfiguration
639 )
640 {
641 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));
642
643 if (SystemConfiguration->PchAzalia == 0) {
644 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));
645 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));
646 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));
647 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));
648 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));
649 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));
650 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));
ConfigureSciSmiGpioRout(IN EFI_PLATFORM_INFO_HOB * PlatformInfo)651 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));
652 }
653
654 DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));
655
656 return EFI_SUCCESS;
657 }
658
659 EFI_STATUS
660 ConfigureSciSmiGpioRout (
661 IN EFI_PLATFORM_INFO_HOB *PlatformInfo)
662 {
663 UINT32 GPI_Routing;
664
665 GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);
666
667 //
668 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
669 //
670 if(PlatformInfo->BoardRev == 3) {
671 GPI_Routing = GPI_Routing & 0xfffc3ffc;
672 GPI_Routing = GPI_Routing | 0x00024002;
673 }
674
675 //
676 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
677 //
678 else {
ConfigureMipiCsi(VOID)679 GPI_Routing = GPI_Routing & 0x3fff3ffc;
680 GPI_Routing = GPI_Routing | 0x80004002;
681 }
682 MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);
683
684 return EFI_SUCCESS;
685 }
686
687 EFI_STATUS
688 ConfigureMipiCsi (
689 VOID)
690 {
691 //
692 //Configure the platform clock for MIPI-CSI usage
693 //PLT_CLK0
694 //
695 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));
696
697 //
698 //PLT_CLK1
699 //
700 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));
701
ConfigureUSBULPI(VOID)702 //
703 //PLT_CLK2
704 //
705 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));
706
707 return EFI_SUCCESS;
708 }
709
710 EFI_STATUS
711 ConfigureUSBULPI (
712 VOID)
713 {
714 //
715 //Configure USB ULPI
716 //USB_ULPI_0_CLK
717 //
718 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));
719 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));
720
721 //
722 //USB_ULPI_0_DATA0
723 //
724 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));
725 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));
726
727 //
728 //USB_ULPI_0_DATA1
729 //
730 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));
731 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));
732
733 //
734 //USB_ULPI_0_DATA2
735 //
736 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));
737 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));
738
739 //
740 //USB_ULPI_0_DATA3
741 //
742 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));
743 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));
744
745 //
746 //USB_ULPI_0_DATA4
747 //
748 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));
749 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));
750
751 //
752 //USB_ULPI_0_DATA5
753 //
754 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));
755 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));
756
757 //
758 //USB_ULPI_0_DATA6
759 //
760 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));
761 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));
762
763 //
764 //USB_ULPI_0_DATA7
765 //
766 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));
767 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));
768
769 //
770 //USB_ULPI_0_DIR
771 //
772 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));
773 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));
774
775 //
776 //USB_ULPI_0_NXT
777 //
778 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));
779 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));
780
781 //
782 //USB_ULPI_0_STP
783 //
784 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));
785 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));
786
787 //
DisableRTD3(VOID)788 //USB_ULPI_0_REFCLK
789 //
790 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));
791 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));
792
793 return EFI_SUCCESS;
794 }
795
796 EFI_STATUS
797 DisableRTD3 (
798 VOID)
799 {
800 //
801 //Disable RTD3
802 //
803 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));
804 MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));
805
806 return EFI_SUCCESS;
807 }
808
809 /**
810 Platform specific initializations in stage1.
PlatformEarlyInitEntry(IN EFI_PEI_FILE_HANDLE FileHandle,IN CONST EFI_PEI_SERVICES ** PeiServices)811
812 @param FfsHeader Pointer to the PEIM FFS file header.
813 @param PeiServices General purpose services available to every PEIM.
814
815 @retval EFI_SUCCESS Operation completed successfully.
816 @retval Otherwise Platform initialization failed.
817 **/
818 EFI_STATUS
819 EFIAPI
820 PlatformEarlyInitEntry (
821
822 IN EFI_PEI_FILE_HANDLE FileHandle,
823 IN CONST EFI_PEI_SERVICES **PeiServices
824 )
825 {
826 EFI_STATUS Status;
827 SYSTEM_CONFIGURATION SystemConfiguration;
828 EFI_PLATFORM_INFO_HOB *PlatformInfo;
829 EFI_PEI_HOB_POINTERS Hob;
830 EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
831
832 //
833 // Initialize SmbusPolicy PPI
834 //
835 Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);
836 ASSERT_EFI_ERROR (Status);
837
838 //
839 // Initialize Stall PPIs
840 //
841 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);
842 ASSERT_EFI_ERROR (Status);
843
844 //
845 // Initialize platform PPIs
846 //
847 Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);
848 ASSERT_EFI_ERROR (Status);
849
850 //
851 // Variable initialization
852 //
853 ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));
854
855 //
856 // Set the some PCI and chipset range as UC
857 // And align to 1M at leaset
858 //
859 Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
860 ASSERT (Hob.Raw != NULL);
861 PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
862
863 //
864 // Initialize PlatformInfo HOB
865 //
866 MultiPlatformInfoInit(PeiServices, PlatformInfo);
867
868 //
869 // Do basic MCH init
870 //
871 MchInit (PeiServices);
872
873 //
874 // Set the new boot mode
875 //
876 Status = UpdateBootMode (PeiServices, PlatformInfo);
877 ASSERT_EFI_ERROR (Status);
878
879 SetPlatformBootMode (PeiServices, PlatformInfo);
880
881 //
882 // Get setup variable. This can only be done after BootMode is updated
883 //
884 GetSetupVariable (PeiServices, &SystemConfiguration);
885
886 CheckOsSelection(PeiServices, &SystemConfiguration);
887
888 //
889 // Update PlatformInfo HOB according to setup variable
890 //
891 PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);
892
893 InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);
894
895 //
896 // Initialize VlvPolicy PPI
897 //
898 Status = VlvPolicyInit (PeiServices, &SystemConfiguration);
899 ASSERT_EFI_ERROR (Status);
900
901 //
902 // Soc specific GPIO setting
903 //
904 ConfigureSoCGpio(&SystemConfiguration);
905
906 //
907 // Baylake Board specific.
908 //
909 if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||
910 PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||
911 PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||
912 PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||
913 PlatformInfo->BoardId == BOARD_ID_BL_STHI ||
914 PlatformInfo->BoardId == BOARD_ID_BB_RVP ||
915 PlatformInfo->BoardId == BOARD_ID_BS_RVP ||
916 PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||
917 PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||
918 PlatformInfo->BoardId == BOARD_ID_CVH) {
919 ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);
920
921 }
922
923
924 //
925 // Configure LPE
926 // Alpine Valley and Bayley Bay board specific
927 //
928 ConfigureLpeGpio(&SystemConfiguration);
929
930 //
931 // Bayley Bay Board specific.
932 //
933 ConfigureSciSmiGpioRout(PlatformInfo);
934 if (SystemConfiguration.LpssI2C3Enabled == 1) {
935 ConfigureMipiCsi();
936 }
937
938
939 //
940 // Do basic CPU init
941 //
942 Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);
943
944 //
945 // Perform basic SSA related platform initialization
946 //
947 PlatformSsaInit (&SystemConfiguration,PeiServices);
948
949
950 //
951 // Do basic PCH init
952 //
953 Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);
954 ASSERT_EFI_ERROR (Status);
955
956 //
957 // Initialize platform PPIs
958 //
959 Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
960 ASSERT_EFI_ERROR (Status);
961
962 if (PlatformInfo->BoardId != BOARD_ID_CVH) {
963 InstallPlatformClocksNotify (PeiServices);
964 InstallPlatformSysCtrlGPIONotify(PeiServices);
965 }
966
967 //
968 // Initialize platform PPIs
969 //
970 Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
971 ASSERT_EFI_ERROR (Status);
972
973 //
974 // Initialize Measured Boot
975 //
976 Status = MeasuredBootInit (PeiServices, &SystemConfiguration);
977 ASSERT_EFI_ERROR (Status);
978
979 return Status;
980 }
981
982 /**
983
984 Return the mainblockcompact Fv.
985
986 @param FvNumber Our enumeration of the firmware volumes we care about.
FindFv(IN EFI_PEI_FIND_FV_PPI * This,IN CONST EFI_PEI_SERVICES ** PeiServices,IN OUT UINT8 * FvNumber,OUT EFI_FIRMWARE_VOLUME_HEADER ** FVAddress)987
988 @param FvAddress Base Address of the memory containing the firmware volume
989
990 @retval EFI_SUCCESS
991 @retval EFI_NOT_FOUND
992
993 **/
994 EFI_STATUS
995 EFIAPI
996 FindFv (
997 IN EFI_PEI_FIND_FV_PPI *This,
998 IN CONST EFI_PEI_SERVICES **PeiServices,
999 IN OUT UINT8 *FvNumber,
1000 OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress
1001 )
1002 {
1003 //
1004 // At present, we only have one Fv to search
1005 //
1006 if (*FvNumber == 0) {
1007 *FvNumber = 1;
1008 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);
1009 return EFI_SUCCESS;
1010 }
1011 else if (*FvNumber == 1) {
1012 *FvNumber = 2;
1013 *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);
1014 return EFI_SUCCESS;
1015 }
1016 else { // Not the one Fv we care about
1017 return EFI_NOT_FOUND;
1018 }
1019 }
1020
1021 EFI_STATUS
1022 EFIAPI
1023 CpuOnlyReset (
1024 IN CONST EFI_PEI_SERVICES **PeiServices
1025 )
1026 {
1027 // MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
1028 #ifdef __GNUC__
1029 __asm__
1030 (
1031 "xorl %ecx, %ecx\n"
1032 "1:hlt; hlt; hlt\n"
1033 "jmp 1b\n"
1034 );
1035 #else
1036 _asm {
1037 xor ecx, ecx
1038 HltLoop:
1039 hlt
1040 hlt
1041 hlt
1042 loop HltLoop
1043 }
1044 #endif
1045 //
1046 // If we get here we need to mark it as a failure.
1047 //
1048 return EFI_UNSUPPORTED;
1049 }
1050
1051
1052 #ifdef __GNUC__
1053 #pragma GCC pop_options
1054 #else
1055 #pragma optimize ("", on)
1056 #endif
1057