1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "mcasmparser"
11 
12 #include "Hexagon.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonTargetStreamer.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
16 #include "MCTargetDesc/HexagonMCAsmInfo.h"
17 #include "MCTargetDesc/HexagonMCChecker.h"
18 #include "MCTargetDesc/HexagonMCELFStreamer.h"
19 #include "MCTargetDesc/HexagonMCExpr.h"
20 #include "MCTargetDesc/HexagonMCShuffler.h"
21 #include "MCTargetDesc/HexagonMCTargetDesc.h"
22 #include "MCTargetDesc/HexagonShuffler.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCELFStreamer.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/MC/MCValue.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/Format.h"
42 #include "llvm/Support/MemoryBuffer.h"
43 #include "llvm/Support/SourceMgr.h"
44 #include "llvm/Support/TargetRegistry.h"
45 #include "llvm/Support/raw_ostream.h"
46 
47 using namespace llvm;
48 
49 static cl::opt<bool> EnableFutureRegs("mfuture-regs",
50                                       cl::desc("Enable future registers"));
51 
52 static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis",
53 cl::desc("Warn for missing parenthesis around predicate registers"),
54 cl::init(true));
55 static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis",
56 cl::desc("Error for missing parenthesis around predicate registers"),
57 cl::init(false));
58 static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch",
59 cl::desc("Warn for mismatching a signed and unsigned value"),
60 cl::init(true));
61 static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register",
62 cl::desc("Warn for register names that arent contigious"),
63 cl::init(true));
64 static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register",
65 cl::desc("Error for register names that aren't contigious"),
66 cl::init(false));
67 
68 
69 namespace {
70 struct HexagonOperand;
71 
72 class HexagonAsmParser : public MCTargetAsmParser {
73 
getTargetStreamer()74   HexagonTargetStreamer &getTargetStreamer() {
75     MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
76     return static_cast<HexagonTargetStreamer &>(TS);
77   }
78 
79   MCAsmParser &Parser;
80   MCAssembler *Assembler;
81   MCInstrInfo const &MCII;
82   MCInst MCB;
83   bool InBrackets;
84 
getParser() const85   MCAsmParser &getParser() const { return Parser; }
getAssembler() const86   MCAssembler *getAssembler() const { return Assembler; }
getLexer() const87   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
88 
equalIsAsmAssignment()89   bool equalIsAsmAssignment() override { return false; }
90   bool isLabel(AsmToken &Token) override;
91 
Warning(SMLoc L,const Twine & Msg)92   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
Error(SMLoc L,const Twine & Msg)93   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
94   bool ParseDirectiveFalign(unsigned Size, SMLoc L);
95 
96   virtual bool ParseRegister(unsigned &RegNo,
97                              SMLoc &StartLoc,
98                              SMLoc &EndLoc) override;
99   bool ParseDirectiveSubsection(SMLoc L);
100   bool ParseDirectiveValue(unsigned Size, SMLoc L);
101   bool ParseDirectiveComm(bool IsLocal, SMLoc L);
102   bool RegisterMatchesArch(unsigned MatchNum) const;
103 
104   bool matchBundleOptions();
105   bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
106   bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
107   void canonicalizeImmediates(MCInst &MCI);
108   bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
109                            OperandVector &InstOperands, uint64_t &ErrorInfo,
110                            bool MatchingInlineAsm);
111 
112   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
113                                OperandVector &Operands, MCStreamer &Out,
114                                uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
115 
116   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
117   void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
118   int processInstruction(MCInst &Inst, OperandVector const &Operands,
119                          SMLoc IDLoc);
120 
121   // Check if we have an assembler and, if so, set the ELF e_header flags.
chksetELFHeaderEFlags(unsigned flags)122   void chksetELFHeaderEFlags(unsigned flags) {
123     if (getAssembler())
124       getAssembler()->setELFHeaderEFlags(flags);
125   }
126 
127   unsigned matchRegister(StringRef Name);
128 
129 /// @name Auto-generated Match Functions
130 /// {
131 
132 #define GET_ASSEMBLER_HEADER
133 #include "HexagonGenAsmMatcher.inc"
134 
135   /// }
136 
137 public:
HexagonAsmParser(const MCSubtargetInfo & _STI,MCAsmParser & _Parser,const MCInstrInfo & MII,const MCTargetOptions & Options)138   HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
139                    const MCInstrInfo &MII, const MCTargetOptions &Options)
140     : MCTargetAsmParser(Options, _STI), Parser(_Parser),
141       MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
142     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
143 
144   MCAsmParserExtension::Initialize(_Parser);
145 
146   Assembler = nullptr;
147   // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
148   if (!Parser.getStreamer().hasRawTextSupport()) {
149     MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
150     Assembler = &MES->getAssembler();
151   }
152   }
153 
154   bool splitIdentifier(OperandVector &Operands);
155   bool parseOperand(OperandVector &Operands);
156   bool parseInstruction(OperandVector &Operands);
157   bool implicitExpressionLocation(OperandVector &Operands);
158   bool parseExpressionOrOperand(OperandVector &Operands);
159   bool parseExpression(MCExpr const *& Expr);
ParseInstruction(ParseInstructionInfo & Info,StringRef Name,SMLoc NameLoc,OperandVector & Operands)160   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
161                                 SMLoc NameLoc, OperandVector &Operands) override
162   {
163     llvm_unreachable("Unimplemented");
164   }
165   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
166                                 AsmToken ID, OperandVector &Operands) override;
167 
168   virtual bool ParseDirective(AsmToken DirectiveID) override;
169 };
170 
171 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
172 /// instruction.
173 struct HexagonOperand : public MCParsedAsmOperand {
174   enum KindTy { Token, Immediate, Register } Kind;
175 
176   SMLoc StartLoc, EndLoc;
177 
178   struct TokTy {
179     const char *Data;
180     unsigned Length;
181   };
182 
183   struct RegTy {
184     unsigned RegNum;
185   };
186 
187   struct ImmTy {
188     const MCExpr *Val;
189   };
190 
191   struct InstTy {
192     OperandVector *SubInsts;
193   };
194 
195   union {
196     struct TokTy Tok;
197     struct RegTy Reg;
198     struct ImmTy Imm;
199   };
200 
HexagonOperand__anon13e295d60111::HexagonOperand201   HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
202 
203 public:
HexagonOperand__anon13e295d60111::HexagonOperand204   HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
205     Kind = o.Kind;
206     StartLoc = o.StartLoc;
207     EndLoc = o.EndLoc;
208     switch (Kind) {
209     case Register:
210       Reg = o.Reg;
211       break;
212     case Immediate:
213       Imm = o.Imm;
214       break;
215     case Token:
216       Tok = o.Tok;
217       break;
218     }
219   }
220 
221   /// getStartLoc - Get the location of the first token of this operand.
getStartLoc__anon13e295d60111::HexagonOperand222   SMLoc getStartLoc() const { return StartLoc; }
223 
224   /// getEndLoc - Get the location of the last token of this operand.
getEndLoc__anon13e295d60111::HexagonOperand225   SMLoc getEndLoc() const { return EndLoc; }
226 
getReg__anon13e295d60111::HexagonOperand227   unsigned getReg() const {
228     assert(Kind == Register && "Invalid access!");
229     return Reg.RegNum;
230   }
231 
getImm__anon13e295d60111::HexagonOperand232   const MCExpr *getImm() const {
233     assert(Kind == Immediate && "Invalid access!");
234     return Imm.Val;
235   }
236 
isToken__anon13e295d60111::HexagonOperand237   bool isToken() const { return Kind == Token; }
isImm__anon13e295d60111::HexagonOperand238   bool isImm() const { return Kind == Immediate; }
isMem__anon13e295d60111::HexagonOperand239   bool isMem() const { llvm_unreachable("No isMem"); }
isReg__anon13e295d60111::HexagonOperand240   bool isReg() const { return Kind == Register; }
241 
CheckImmRange__anon13e295d60111::HexagonOperand242   bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
243                      bool isRelocatable, bool Extendable) const {
244     if (Kind == Immediate) {
245       const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm());
246       if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable)
247         return false;
248       int64_t Res;
249       if (myMCExpr->evaluateAsAbsolute(Res)) {
250         int bits = immBits + zeroBits;
251         // Field bit range is zerobits + bits
252         // zeroBits must be 0
253         if (Res & ((1 << zeroBits) - 1))
254           return false;
255         if (isSigned) {
256           if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
257             return true;
258         } else {
259           if (bits == 64)
260             return true;
261           if (Res >= 0)
262             return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false;
263           else {
264             const int64_t high_bit_set = 1ULL << 63;
265             const uint64_t mask = (high_bit_set >> (63 - bits));
266             return (((uint64_t)Res & mask) == mask) ? true : false;
267           }
268         }
269       } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
270         return true;
271       else if (myMCExpr->getKind() == MCExpr::Binary ||
272                myMCExpr->getKind() == MCExpr::Unary)
273         return true;
274     }
275     return false;
276   }
277 
isf32Ext__anon13e295d60111::HexagonOperand278   bool isf32Ext() const { return false; }
iss32Imm__anon13e295d60111::HexagonOperand279   bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); }
iss23_2Imm__anon13e295d60111::HexagonOperand280   bool iss23_2Imm() const { return CheckImmRange(23, 2, true, true, false); }
iss8Imm__anon13e295d60111::HexagonOperand281   bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); }
iss8Imm64__anon13e295d60111::HexagonOperand282   bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); }
iss7Imm__anon13e295d60111::HexagonOperand283   bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); }
iss6Imm__anon13e295d60111::HexagonOperand284   bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); }
iss4Imm__anon13e295d60111::HexagonOperand285   bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); }
iss4_0Imm__anon13e295d60111::HexagonOperand286   bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
iss4_1Imm__anon13e295d60111::HexagonOperand287   bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
iss4_2Imm__anon13e295d60111::HexagonOperand288   bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
iss4_3Imm__anon13e295d60111::HexagonOperand289   bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
iss4_6Imm__anon13e295d60111::HexagonOperand290   bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
iss3_6Imm__anon13e295d60111::HexagonOperand291   bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
iss3Imm__anon13e295d60111::HexagonOperand292   bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); }
293 
isu64Imm__anon13e295d60111::HexagonOperand294   bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); }
isu32Imm__anon13e295d60111::HexagonOperand295   bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); }
isu26_6Imm__anon13e295d60111::HexagonOperand296   bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
isu16Imm__anon13e295d60111::HexagonOperand297   bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); }
isu16_0Imm__anon13e295d60111::HexagonOperand298   bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
isu16_1Imm__anon13e295d60111::HexagonOperand299   bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
isu16_2Imm__anon13e295d60111::HexagonOperand300   bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
isu16_3Imm__anon13e295d60111::HexagonOperand301   bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
isu11_3Imm__anon13e295d60111::HexagonOperand302   bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
isu6_0Imm__anon13e295d60111::HexagonOperand303   bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
isu6_1Imm__anon13e295d60111::HexagonOperand304   bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
isu6_2Imm__anon13e295d60111::HexagonOperand305   bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
isu6_3Imm__anon13e295d60111::HexagonOperand306   bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
isu10Imm__anon13e295d60111::HexagonOperand307   bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); }
isu9Imm__anon13e295d60111::HexagonOperand308   bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); }
isu8Imm__anon13e295d60111::HexagonOperand309   bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); }
isu7Imm__anon13e295d60111::HexagonOperand310   bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); }
isu6Imm__anon13e295d60111::HexagonOperand311   bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); }
isu5Imm__anon13e295d60111::HexagonOperand312   bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); }
isu4Imm__anon13e295d60111::HexagonOperand313   bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); }
isu3Imm__anon13e295d60111::HexagonOperand314   bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); }
isu2Imm__anon13e295d60111::HexagonOperand315   bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); }
isu1Imm__anon13e295d60111::HexagonOperand316   bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); }
317 
ism6Imm__anon13e295d60111::HexagonOperand318   bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); }
isn8Imm__anon13e295d60111::HexagonOperand319   bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); }
320 
iss16Ext__anon13e295d60111::HexagonOperand321   bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
iss12Ext__anon13e295d60111::HexagonOperand322   bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
iss10Ext__anon13e295d60111::HexagonOperand323   bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }
iss9Ext__anon13e295d60111::HexagonOperand324   bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }
iss8Ext__anon13e295d60111::HexagonOperand325   bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }
iss7Ext__anon13e295d60111::HexagonOperand326   bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }
iss6Ext__anon13e295d60111::HexagonOperand327   bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }
iss11_0Ext__anon13e295d60111::HexagonOperand328   bool iss11_0Ext() const {
329     return CheckImmRange(11 + 26, 0, true, true, true);
330   }
iss11_1Ext__anon13e295d60111::HexagonOperand331   bool iss11_1Ext() const {
332     return CheckImmRange(11 + 26, 1, true, true, true);
333   }
iss11_2Ext__anon13e295d60111::HexagonOperand334   bool iss11_2Ext() const {
335     return CheckImmRange(11 + 26, 2, true, true, true);
336   }
iss11_3Ext__anon13e295d60111::HexagonOperand337   bool iss11_3Ext() const {
338     return CheckImmRange(11 + 26, 3, true, true, true);
339   }
340 
isu6Ext__anon13e295d60111::HexagonOperand341   bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
isu7Ext__anon13e295d60111::HexagonOperand342   bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }
isu8Ext__anon13e295d60111::HexagonOperand343   bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }
isu9Ext__anon13e295d60111::HexagonOperand344   bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }
isu10Ext__anon13e295d60111::HexagonOperand345   bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }
isu6_0Ext__anon13e295d60111::HexagonOperand346   bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
isu6_1Ext__anon13e295d60111::HexagonOperand347   bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }
isu6_2Ext__anon13e295d60111::HexagonOperand348   bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }
isu6_3Ext__anon13e295d60111::HexagonOperand349   bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }
isu32MustExt__anon13e295d60111::HexagonOperand350   bool isu32MustExt() const { return isImm(); }
351 
addRegOperands__anon13e295d60111::HexagonOperand352   void addRegOperands(MCInst &Inst, unsigned N) const {
353     assert(N == 1 && "Invalid number of operands!");
354     Inst.addOperand(MCOperand::createReg(getReg()));
355   }
356 
addImmOperands__anon13e295d60111::HexagonOperand357   void addImmOperands(MCInst &Inst, unsigned N) const {
358     assert(N == 1 && "Invalid number of operands!");
359     Inst.addOperand(MCOperand::createExpr(getImm()));
360   }
361 
addSignedImmOperands__anon13e295d60111::HexagonOperand362   void addSignedImmOperands(MCInst &Inst, unsigned N) const {
363     assert(N == 1 && "Invalid number of operands!");
364     HexagonMCExpr *Expr =
365         const_cast<HexagonMCExpr *>(cast<HexagonMCExpr>(getImm()));
366     int64_t Value;
367     if (!Expr->evaluateAsAbsolute(Value)) {
368       Inst.addOperand(MCOperand::createExpr(Expr));
369       return;
370     }
371     int64_t Extended = SignExtend64(Value, 32);
372     if ((Extended < 0) != (Value < 0))
373       Expr->setSignMismatch();
374     Inst.addOperand(MCOperand::createExpr(Expr));
375   }
376 
addf32ExtOperands__anon13e295d60111::HexagonOperand377   void addf32ExtOperands(MCInst &Inst, unsigned N) const {
378     addImmOperands(Inst, N);
379   }
380 
adds32ImmOperands__anon13e295d60111::HexagonOperand381   void adds32ImmOperands(MCInst &Inst, unsigned N) const {
382     addSignedImmOperands(Inst, N);
383   }
adds23_2ImmOperands__anon13e295d60111::HexagonOperand384   void adds23_2ImmOperands(MCInst &Inst, unsigned N) const {
385     addSignedImmOperands(Inst, N);
386   }
adds8ImmOperands__anon13e295d60111::HexagonOperand387   void adds8ImmOperands(MCInst &Inst, unsigned N) const {
388     addSignedImmOperands(Inst, N);
389   }
adds8Imm64Operands__anon13e295d60111::HexagonOperand390   void adds8Imm64Operands(MCInst &Inst, unsigned N) const {
391     addSignedImmOperands(Inst, N);
392   }
adds6ImmOperands__anon13e295d60111::HexagonOperand393   void adds6ImmOperands(MCInst &Inst, unsigned N) const {
394     addSignedImmOperands(Inst, N);
395   }
adds4ImmOperands__anon13e295d60111::HexagonOperand396   void adds4ImmOperands(MCInst &Inst, unsigned N) const {
397     addSignedImmOperands(Inst, N);
398   }
adds4_0ImmOperands__anon13e295d60111::HexagonOperand399   void adds4_0ImmOperands(MCInst &Inst, unsigned N) const {
400     addSignedImmOperands(Inst, N);
401   }
adds4_1ImmOperands__anon13e295d60111::HexagonOperand402   void adds4_1ImmOperands(MCInst &Inst, unsigned N) const {
403     addSignedImmOperands(Inst, N);
404   }
adds4_2ImmOperands__anon13e295d60111::HexagonOperand405   void adds4_2ImmOperands(MCInst &Inst, unsigned N) const {
406     addSignedImmOperands(Inst, N);
407   }
adds4_3ImmOperands__anon13e295d60111::HexagonOperand408   void adds4_3ImmOperands(MCInst &Inst, unsigned N) const {
409     addSignedImmOperands(Inst, N);
410   }
adds3ImmOperands__anon13e295d60111::HexagonOperand411   void adds3ImmOperands(MCInst &Inst, unsigned N) const {
412     addSignedImmOperands(Inst, N);
413   }
414 
addu64ImmOperands__anon13e295d60111::HexagonOperand415   void addu64ImmOperands(MCInst &Inst, unsigned N) const {
416     addImmOperands(Inst, N);
417   }
addu32ImmOperands__anon13e295d60111::HexagonOperand418   void addu32ImmOperands(MCInst &Inst, unsigned N) const {
419     addImmOperands(Inst, N);
420   }
addu26_6ImmOperands__anon13e295d60111::HexagonOperand421   void addu26_6ImmOperands(MCInst &Inst, unsigned N) const {
422     addImmOperands(Inst, N);
423   }
addu16ImmOperands__anon13e295d60111::HexagonOperand424   void addu16ImmOperands(MCInst &Inst, unsigned N) const {
425     addImmOperands(Inst, N);
426   }
addu16_0ImmOperands__anon13e295d60111::HexagonOperand427   void addu16_0ImmOperands(MCInst &Inst, unsigned N) const {
428     addImmOperands(Inst, N);
429   }
addu16_1ImmOperands__anon13e295d60111::HexagonOperand430   void addu16_1ImmOperands(MCInst &Inst, unsigned N) const {
431     addImmOperands(Inst, N);
432   }
addu16_2ImmOperands__anon13e295d60111::HexagonOperand433   void addu16_2ImmOperands(MCInst &Inst, unsigned N) const {
434     addImmOperands(Inst, N);
435   }
addu16_3ImmOperands__anon13e295d60111::HexagonOperand436   void addu16_3ImmOperands(MCInst &Inst, unsigned N) const {
437     addImmOperands(Inst, N);
438   }
addu11_3ImmOperands__anon13e295d60111::HexagonOperand439   void addu11_3ImmOperands(MCInst &Inst, unsigned N) const {
440     addImmOperands(Inst, N);
441   }
addu10ImmOperands__anon13e295d60111::HexagonOperand442   void addu10ImmOperands(MCInst &Inst, unsigned N) const {
443     addImmOperands(Inst, N);
444   }
addu9ImmOperands__anon13e295d60111::HexagonOperand445   void addu9ImmOperands(MCInst &Inst, unsigned N) const {
446     addImmOperands(Inst, N);
447   }
addu8ImmOperands__anon13e295d60111::HexagonOperand448   void addu8ImmOperands(MCInst &Inst, unsigned N) const {
449     addImmOperands(Inst, N);
450   }
addu7ImmOperands__anon13e295d60111::HexagonOperand451   void addu7ImmOperands(MCInst &Inst, unsigned N) const {
452     addImmOperands(Inst, N);
453   }
addu6ImmOperands__anon13e295d60111::HexagonOperand454   void addu6ImmOperands(MCInst &Inst, unsigned N) const {
455     addImmOperands(Inst, N);
456   }
addu6_0ImmOperands__anon13e295d60111::HexagonOperand457   void addu6_0ImmOperands(MCInst &Inst, unsigned N) const {
458     addImmOperands(Inst, N);
459   }
addu6_1ImmOperands__anon13e295d60111::HexagonOperand460   void addu6_1ImmOperands(MCInst &Inst, unsigned N) const {
461     addImmOperands(Inst, N);
462   }
addu6_2ImmOperands__anon13e295d60111::HexagonOperand463   void addu6_2ImmOperands(MCInst &Inst, unsigned N) const {
464     addImmOperands(Inst, N);
465   }
addu6_3ImmOperands__anon13e295d60111::HexagonOperand466   void addu6_3ImmOperands(MCInst &Inst, unsigned N) const {
467     addImmOperands(Inst, N);
468   }
addu5ImmOperands__anon13e295d60111::HexagonOperand469   void addu5ImmOperands(MCInst &Inst, unsigned N) const {
470     addImmOperands(Inst, N);
471   }
addu4ImmOperands__anon13e295d60111::HexagonOperand472   void addu4ImmOperands(MCInst &Inst, unsigned N) const {
473     addImmOperands(Inst, N);
474   }
addu3ImmOperands__anon13e295d60111::HexagonOperand475   void addu3ImmOperands(MCInst &Inst, unsigned N) const {
476     addImmOperands(Inst, N);
477   }
addu2ImmOperands__anon13e295d60111::HexagonOperand478   void addu2ImmOperands(MCInst &Inst, unsigned N) const {
479     addImmOperands(Inst, N);
480   }
addu1ImmOperands__anon13e295d60111::HexagonOperand481   void addu1ImmOperands(MCInst &Inst, unsigned N) const {
482     addImmOperands(Inst, N);
483   }
484 
addm6ImmOperands__anon13e295d60111::HexagonOperand485   void addm6ImmOperands(MCInst &Inst, unsigned N) const {
486     addImmOperands(Inst, N);
487   }
addn8ImmOperands__anon13e295d60111::HexagonOperand488   void addn8ImmOperands(MCInst &Inst, unsigned N) const {
489     addImmOperands(Inst, N);
490   }
491 
adds16ExtOperands__anon13e295d60111::HexagonOperand492   void adds16ExtOperands(MCInst &Inst, unsigned N) const {
493     addSignedImmOperands(Inst, N);
494   }
adds12ExtOperands__anon13e295d60111::HexagonOperand495   void adds12ExtOperands(MCInst &Inst, unsigned N) const {
496     addSignedImmOperands(Inst, N);
497   }
adds10ExtOperands__anon13e295d60111::HexagonOperand498   void adds10ExtOperands(MCInst &Inst, unsigned N) const {
499     addSignedImmOperands(Inst, N);
500   }
adds9ExtOperands__anon13e295d60111::HexagonOperand501   void adds9ExtOperands(MCInst &Inst, unsigned N) const {
502     addSignedImmOperands(Inst, N);
503   }
adds8ExtOperands__anon13e295d60111::HexagonOperand504   void adds8ExtOperands(MCInst &Inst, unsigned N) const {
505     addSignedImmOperands(Inst, N);
506   }
adds6ExtOperands__anon13e295d60111::HexagonOperand507   void adds6ExtOperands(MCInst &Inst, unsigned N) const {
508     addSignedImmOperands(Inst, N);
509   }
adds11_0ExtOperands__anon13e295d60111::HexagonOperand510   void adds11_0ExtOperands(MCInst &Inst, unsigned N) const {
511     addSignedImmOperands(Inst, N);
512   }
adds11_1ExtOperands__anon13e295d60111::HexagonOperand513   void adds11_1ExtOperands(MCInst &Inst, unsigned N) const {
514     addSignedImmOperands(Inst, N);
515   }
adds11_2ExtOperands__anon13e295d60111::HexagonOperand516   void adds11_2ExtOperands(MCInst &Inst, unsigned N) const {
517     addSignedImmOperands(Inst, N);
518   }
adds11_3ExtOperands__anon13e295d60111::HexagonOperand519   void adds11_3ExtOperands(MCInst &Inst, unsigned N) const {
520     addSignedImmOperands(Inst, N);
521   }
522 
addu6ExtOperands__anon13e295d60111::HexagonOperand523   void addu6ExtOperands(MCInst &Inst, unsigned N) const {
524     addImmOperands(Inst, N);
525   }
addu7ExtOperands__anon13e295d60111::HexagonOperand526   void addu7ExtOperands(MCInst &Inst, unsigned N) const {
527     addImmOperands(Inst, N);
528   }
addu8ExtOperands__anon13e295d60111::HexagonOperand529   void addu8ExtOperands(MCInst &Inst, unsigned N) const {
530     addImmOperands(Inst, N);
531   }
addu9ExtOperands__anon13e295d60111::HexagonOperand532   void addu9ExtOperands(MCInst &Inst, unsigned N) const {
533     addImmOperands(Inst, N);
534   }
addu10ExtOperands__anon13e295d60111::HexagonOperand535   void addu10ExtOperands(MCInst &Inst, unsigned N) const {
536     addImmOperands(Inst, N);
537   }
addu6_0ExtOperands__anon13e295d60111::HexagonOperand538   void addu6_0ExtOperands(MCInst &Inst, unsigned N) const {
539     addImmOperands(Inst, N);
540   }
addu6_1ExtOperands__anon13e295d60111::HexagonOperand541   void addu6_1ExtOperands(MCInst &Inst, unsigned N) const {
542     addImmOperands(Inst, N);
543   }
addu6_2ExtOperands__anon13e295d60111::HexagonOperand544   void addu6_2ExtOperands(MCInst &Inst, unsigned N) const {
545     addImmOperands(Inst, N);
546   }
addu6_3ExtOperands__anon13e295d60111::HexagonOperand547   void addu6_3ExtOperands(MCInst &Inst, unsigned N) const {
548     addImmOperands(Inst, N);
549   }
addu32MustExtOperands__anon13e295d60111::HexagonOperand550   void addu32MustExtOperands(MCInst &Inst, unsigned N) const {
551     addImmOperands(Inst, N);
552   }
553 
adds4_6ImmOperands__anon13e295d60111::HexagonOperand554   void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {
555     assert(N == 1 && "Invalid number of operands!");
556     const MCConstantExpr *CE =
557         dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
558     Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
559   }
560 
adds3_6ImmOperands__anon13e295d60111::HexagonOperand561   void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {
562     assert(N == 1 && "Invalid number of operands!");
563     const MCConstantExpr *CE =
564         dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
565     Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
566   }
567 
getToken__anon13e295d60111::HexagonOperand568   StringRef getToken() const {
569     assert(Kind == Token && "Invalid access!");
570     return StringRef(Tok.Data, Tok.Length);
571   }
572 
573   virtual void print(raw_ostream &OS) const;
574 
CreateToken__anon13e295d60111::HexagonOperand575   static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {
576     HexagonOperand *Op = new HexagonOperand(Token);
577     Op->Tok.Data = Str.data();
578     Op->Tok.Length = Str.size();
579     Op->StartLoc = S;
580     Op->EndLoc = S;
581     return std::unique_ptr<HexagonOperand>(Op);
582   }
583 
CreateReg__anon13e295d60111::HexagonOperand584   static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
585                                                    SMLoc E) {
586     HexagonOperand *Op = new HexagonOperand(Register);
587     Op->Reg.RegNum = RegNum;
588     Op->StartLoc = S;
589     Op->EndLoc = E;
590     return std::unique_ptr<HexagonOperand>(Op);
591   }
592 
CreateImm__anon13e295d60111::HexagonOperand593   static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,
594                                                    SMLoc E) {
595     HexagonOperand *Op = new HexagonOperand(Immediate);
596     Op->Imm.Val = Val;
597     Op->StartLoc = S;
598     Op->EndLoc = E;
599     return std::unique_ptr<HexagonOperand>(Op);
600   }
601 };
602 
603 } // end anonymous namespace.
604 
print(raw_ostream & OS) const605 void HexagonOperand::print(raw_ostream &OS) const {
606   switch (Kind) {
607   case Immediate:
608     getImm()->print(OS, nullptr);
609     break;
610   case Register:
611     OS << "<register R";
612     OS << getReg() << ">";
613     break;
614   case Token:
615     OS << "'" << getToken() << "'";
616     break;
617   }
618 }
619 
finishBundle(SMLoc IDLoc,MCStreamer & Out)620 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
621   DEBUG(dbgs() << "Bundle:");
622   DEBUG(MCB.dump_pretty(dbgs()));
623   DEBUG(dbgs() << "--\n");
624 
625   // Check the bundle for errors.
626   const MCRegisterInfo *RI = getContext().getRegisterInfo();
627   HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI);
628 
629   bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
630                                                         getContext(), MCB,
631                                                         &Check);
632 
633   while (Check.getNextErrInfo() == true) {
634     unsigned Reg = Check.getErrRegister();
635     Twine R(RI->getName(Reg));
636 
637     uint64_t Err = Check.getError();
638     if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {
639       if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)
640         Error(IDLoc,
641               "unconditional branch cannot precede another branch in packet");
642 
643       if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||
644           HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)
645         Error(IDLoc, "register `" + R +
646                          "' used with `.new' "
647                          "but not validly modified in the same packet");
648 
649       if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)
650         Error(IDLoc, "register `" + R + "' modified more than once");
651 
652       if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)
653         Error(IDLoc, "cannot write to read-only register `" + R + "'");
654 
655       if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)
656         Error(IDLoc, "loop-setup and some branch instructions "
657                      "cannot be in the same packet");
658 
659       if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {
660         Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');
661         Error(IDLoc, "packet marked with `:endloop" + N + "' " +
662                          "cannot contain instructions that modify register " +
663                          "`" + R + "'");
664       }
665 
666       if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)
667         Error(IDLoc,
668               "instruction cannot appear in packet with other instructions");
669 
670       if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)
671         Error(IDLoc, "too many slots used in packet");
672 
673       if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {
674         uint64_t Erm = Check.getShuffleError();
675 
676         if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)
677           Error(IDLoc, "invalid instruction packet");
678         else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)
679           Error(IDLoc, "invalid instruction packet: too many stores");
680         else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)
681           Error(IDLoc, "invalid instruction packet: too many loads");
682         else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)
683           Error(IDLoc, "too many branches in packet");
684         else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)
685           Error(IDLoc, "invalid instruction packet: out of slots");
686         else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)
687           Error(IDLoc, "invalid instruction packet: slot error");
688         else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)
689           Error(IDLoc, "v60 packet violation");
690         else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)
691           Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
692         else
693           Error(IDLoc, "unknown error in instruction packet");
694       }
695     }
696 
697     unsigned Warn = Check.getWarning();
698     if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) {
699       if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn)
700         Warning(IDLoc, "register `" + R + "' used with `.cur' "
701                                           "but not used in the same packet");
702       else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn)
703         Warning(IDLoc, "register `" + R + "' used with `.tmp' "
704                                           "but not used in the same packet");
705     }
706   }
707 
708   if (CheckOk) {
709     MCB.setLoc(IDLoc);
710     if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
711       assert(!HexagonMCInstrInfo::isInnerLoop(MCB));
712       assert(!HexagonMCInstrInfo::isOuterLoop(MCB));
713       // Empty packets are valid yet aren't emitted
714       return false;
715     }
716     Out.EmitInstruction(MCB, getSTI());
717   } else {
718     // If compounding and duplexing didn't reduce the size below
719     // 4 or less we have a packet that is too big.
720     if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
721       Error(IDLoc, "invalid instruction packet: out of slots");
722       return true; // Error
723     }
724   }
725 
726   return false; // No error
727 }
728 
matchBundleOptions()729 bool HexagonAsmParser::matchBundleOptions() {
730   MCAsmParser &Parser = getParser();
731   while (true) {
732     if (!Parser.getTok().is(AsmToken::Colon))
733       return false;
734     Lex();
735     StringRef Option = Parser.getTok().getString();
736     if (Option.compare_lower("endloop0") == 0)
737       HexagonMCInstrInfo::setInnerLoop(MCB);
738     else if (Option.compare_lower("endloop1") == 0)
739       HexagonMCInstrInfo::setOuterLoop(MCB);
740     else if (Option.compare_lower("mem_noshuf") == 0)
741       HexagonMCInstrInfo::setMemReorderDisabled(MCB);
742     else if (Option.compare_lower("mem_shuf") == 0)
743       HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB);
744     else
745       return true;
746     Lex();
747   }
748 }
749 
750 // For instruction aliases, immediates are generated rather than
751 // MCConstantExpr.  Convert them for uniform MCExpr.
752 // Also check for signed/unsigned mismatches and warn
canonicalizeImmediates(MCInst & MCI)753 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
754   MCInst NewInst;
755   NewInst.setOpcode(MCI.getOpcode());
756   for (MCOperand &I : MCI)
757     if (I.isImm()) {
758       int64_t Value (I.getImm());
759       NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
760           MCConstantExpr::create(Value, getContext()), getContext())));
761     }
762     else {
763       if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
764           WarnSignedMismatch)
765         Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
766       NewInst.addOperand(I);
767     }
768   MCI = NewInst;
769 }
770 
matchOneInstruction(MCInst & MCI,SMLoc IDLoc,OperandVector & InstOperands,uint64_t & ErrorInfo,bool MatchingInlineAsm)771 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
772                                            OperandVector &InstOperands,
773                                            uint64_t &ErrorInfo,
774                                            bool MatchingInlineAsm) {
775   // Perform matching with tablegen asmmatcher generated function
776   int result =
777       MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
778   if (result == Match_Success) {
779     MCI.setLoc(IDLoc);
780     canonicalizeImmediates(MCI);
781     result = processInstruction(MCI, InstOperands, IDLoc);
782 
783     DEBUG(dbgs() << "Insn:");
784     DEBUG(MCI.dump_pretty(dbgs()));
785     DEBUG(dbgs() << "\n\n");
786 
787     MCI.setLoc(IDLoc);
788   }
789 
790   // Create instruction operand for bundle instruction
791   //   Break this into a separate function Code here is less readable
792   //   Think about how to get an instruction error to report correctly.
793   //   SMLoc will return the "{"
794   switch (result) {
795   default:
796     break;
797   case Match_Success:
798     return false;
799   case Match_MissingFeature:
800     return Error(IDLoc, "invalid instruction");
801   case Match_MnemonicFail:
802     return Error(IDLoc, "unrecognized instruction");
803   case Match_InvalidOperand:
804     SMLoc ErrorLoc = IDLoc;
805     if (ErrorInfo != ~0U) {
806       if (ErrorInfo >= InstOperands.size())
807         return Error(IDLoc, "too few operands for instruction");
808 
809       ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
810                      ->getStartLoc();
811       if (ErrorLoc == SMLoc())
812         ErrorLoc = IDLoc;
813     }
814     return Error(ErrorLoc, "invalid operand for instruction");
815   }
816   llvm_unreachable("Implement any new match types added!");
817 }
818 
MatchAndEmitInstruction(SMLoc IDLoc,unsigned & Opcode,OperandVector & Operands,MCStreamer & Out,uint64_t & ErrorInfo,bool MatchingInlineAsm)819 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
820                                                OperandVector &Operands,
821                                                MCStreamer &Out,
822                                                uint64_t &ErrorInfo,
823                                                bool MatchingInlineAsm) {
824   if (!InBrackets) {
825     MCB.clear();
826     MCB.addOperand(MCOperand::createImm(0));
827   }
828   HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
829   if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
830     assert(Operands.size() == 1 && "Brackets should be by themselves");
831     if (InBrackets) {
832       getParser().Error(IDLoc, "Already in a packet");
833       return true;
834     }
835     InBrackets = true;
836     return false;
837   }
838   if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
839     assert(Operands.size() == 1 && "Brackets should be by themselves");
840     if (!InBrackets) {
841       getParser().Error(IDLoc, "Not in a packet");
842       return true;
843     }
844     InBrackets = false;
845     if (matchBundleOptions())
846       return true;
847     return finishBundle(IDLoc, Out);
848   }
849   MCInst *SubInst = new (getParser().getContext()) MCInst;
850   if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
851                           MatchingInlineAsm))
852     return true;
853   HexagonMCInstrInfo::extendIfNeeded(
854       getParser().getContext(), MCII, MCB, *SubInst);
855   MCB.addOperand(MCOperand::createInst(SubInst));
856   if (!InBrackets)
857     return finishBundle(IDLoc, Out);
858   return false;
859 }
860 
861 /// ParseDirective parses the Hexagon specific directives
ParseDirective(AsmToken DirectiveID)862 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
863   StringRef IDVal = DirectiveID.getIdentifier();
864   if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte"))
865     return ParseDirectiveValue(4, DirectiveID.getLoc());
866   if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" ||
867       IDVal.lower() == ".half")
868     return ParseDirectiveValue(2, DirectiveID.getLoc());
869   if (IDVal.lower() == ".falign")
870     return ParseDirectiveFalign(256, DirectiveID.getLoc());
871   if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
872     return ParseDirectiveComm(true, DirectiveID.getLoc());
873   if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
874     return ParseDirectiveComm(false, DirectiveID.getLoc());
875   if (IDVal.lower() == ".subsection")
876     return ParseDirectiveSubsection(DirectiveID.getLoc());
877 
878   return true;
879 }
ParseDirectiveSubsection(SMLoc L)880 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
881   const MCExpr *Subsection = 0;
882   int64_t Res;
883 
884   assert((getLexer().isNot(AsmToken::EndOfStatement)) &&
885          "Invalid subsection directive");
886   getParser().parseExpression(Subsection);
887 
888   if (!Subsection->evaluateAsAbsolute(Res))
889     return Error(L, "Cannot evaluate subsection number");
890 
891   if (getLexer().isNot(AsmToken::EndOfStatement))
892     return TokError("unexpected token in directive");
893 
894   // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
895   // negative subsections together and in the same order but at the opposite
896   // end of the section.  Only legacy hexagon-gcc created assembly code
897   // used negative subsections.
898   if ((Res < 0) && (Res > -8193))
899     Subsection = HexagonMCExpr::create(
900         MCConstantExpr::create(8192 + Res, getContext()), getContext());
901 
902   getStreamer().SubSection(Subsection);
903   return false;
904 }
905 
906 ///  ::= .falign [expression]
ParseDirectiveFalign(unsigned Size,SMLoc L)907 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
908 
909   int64_t MaxBytesToFill = 15;
910 
911   // if there is an arguement
912   if (getLexer().isNot(AsmToken::EndOfStatement)) {
913     const MCExpr *Value;
914     SMLoc ExprLoc = L;
915 
916     // Make sure we have a number (false is returned if expression is a number)
917     if (getParser().parseExpression(Value) == false) {
918       // Make sure this is a number that is in range
919       const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);
920       uint64_t IntValue = MCE->getValue();
921       if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
922         return Error(ExprLoc, "literal value out of range (256) for falign");
923       MaxBytesToFill = IntValue;
924       Lex();
925     } else {
926       return Error(ExprLoc, "not a valid expression for falign directive");
927     }
928   }
929 
930   getTargetStreamer().emitFAlign(16, MaxBytesToFill);
931   Lex();
932 
933   return false;
934 }
935 
936 ///  ::= .word [ expression (, expression)* ]
ParseDirectiveValue(unsigned Size,SMLoc L)937 bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) {
938   if (getLexer().isNot(AsmToken::EndOfStatement)) {
939 
940     for (;;) {
941       const MCExpr *Value;
942       SMLoc ExprLoc = L;
943       if (getParser().parseExpression(Value))
944         return true;
945 
946       // Special case constant expressions to match code generator.
947       if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) {
948         assert(Size <= 8 && "Invalid size");
949         uint64_t IntValue = MCE->getValue();
950         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
951           return Error(ExprLoc, "literal value out of range for directive");
952         getStreamer().EmitIntValue(IntValue, Size);
953       } else
954         getStreamer().EmitValue(Value, Size);
955 
956       if (getLexer().is(AsmToken::EndOfStatement))
957         break;
958 
959       // FIXME: Improve diagnostic.
960       if (getLexer().isNot(AsmToken::Comma))
961         return TokError("unexpected token in directive");
962       Lex();
963     }
964   }
965 
966   Lex();
967   return false;
968 }
969 
970 // This is largely a copy of AsmParser's ParseDirectiveComm extended to
971 // accept a 3rd argument, AccessAlignment which indicates the smallest
972 // memory access made to the symbol, expressed in bytes.  If no
973 // AccessAlignment is specified it defaults to the Alignment Value.
974 // Hexagon's .lcomm:
975 //   .lcomm Symbol, Length, Alignment, AccessAlignment
ParseDirectiveComm(bool IsLocal,SMLoc Loc)976 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
977   // FIXME: need better way to detect if AsmStreamer (upstream removed
978   // getKind())
979   if (getStreamer().hasRawTextSupport())
980     return true; // Only object file output requires special treatment.
981 
982   StringRef Name;
983   if (getParser().parseIdentifier(Name))
984     return TokError("expected identifier in directive");
985   // Handle the identifier as the key symbol.
986   MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
987 
988   if (getLexer().isNot(AsmToken::Comma))
989     return TokError("unexpected token in directive");
990   Lex();
991 
992   int64_t Size;
993   SMLoc SizeLoc = getLexer().getLoc();
994   if (getParser().parseAbsoluteExpression(Size))
995     return true;
996 
997   int64_t ByteAlignment = 1;
998   SMLoc ByteAlignmentLoc;
999   if (getLexer().is(AsmToken::Comma)) {
1000     Lex();
1001     ByteAlignmentLoc = getLexer().getLoc();
1002     if (getParser().parseAbsoluteExpression(ByteAlignment))
1003       return true;
1004     if (!isPowerOf2_64(ByteAlignment))
1005       return Error(ByteAlignmentLoc, "alignment must be a power of 2");
1006   }
1007 
1008   int64_t AccessAlignment = 0;
1009   if (getLexer().is(AsmToken::Comma)) {
1010     // The optional access argument specifies the size of the smallest memory
1011     //   access to be made to the symbol, expressed in bytes.
1012     SMLoc AccessAlignmentLoc;
1013     Lex();
1014     AccessAlignmentLoc = getLexer().getLoc();
1015     if (getParser().parseAbsoluteExpression(AccessAlignment))
1016       return true;
1017 
1018     if (!isPowerOf2_64(AccessAlignment))
1019       return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
1020   }
1021 
1022   if (getLexer().isNot(AsmToken::EndOfStatement))
1023     return TokError("unexpected token in '.comm' or '.lcomm' directive");
1024 
1025   Lex();
1026 
1027   // NOTE: a size of zero for a .comm should create a undefined symbol
1028   // but a size of .lcomm creates a bss symbol of size zero.
1029   if (Size < 0)
1030     return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
1031                           "be less than zero");
1032 
1033   // NOTE: The alignment in the directive is a power of 2 value, the assembler
1034   // may internally end up wanting an alignment in bytes.
1035   // FIXME: Diagnose overflow.
1036   if (ByteAlignment < 0)
1037     return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
1038                                    "alignment, can't be less than zero");
1039 
1040   if (!Sym->isUndefined())
1041     return Error(Loc, "invalid symbol redefinition");
1042 
1043   HexagonMCELFStreamer &HexagonELFStreamer =
1044       static_cast<HexagonMCELFStreamer &>(getStreamer());
1045   if (IsLocal) {
1046     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
1047                                                       AccessAlignment);
1048     return false;
1049   }
1050 
1051   HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
1052                                                AccessAlignment);
1053   return false;
1054 }
1055 
1056 // validate register against architecture
RegisterMatchesArch(unsigned MatchNum) const1057 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
1058   return true;
1059 }
1060 
1061 // extern "C" void LLVMInitializeHexagonAsmLexer();
1062 
1063 /// Force static initialization.
LLVMInitializeHexagonAsmParser()1064 extern "C" void LLVMInitializeHexagonAsmParser() {
1065   RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget);
1066 }
1067 
1068 #define GET_MATCHER_IMPLEMENTATION
1069 #define GET_REGISTER_MATCHER
1070 #include "HexagonGenAsmMatcher.inc"
1071 
1072 namespace {
previousEqual(OperandVector & Operands,size_t Index,StringRef String)1073 bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) {
1074   if (Index >= Operands.size())
1075     return false;
1076   MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
1077   if (!Operand.isToken())
1078     return false;
1079   return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);
1080 }
previousIsLoop(OperandVector & Operands,size_t Index)1081 bool previousIsLoop(OperandVector &Operands, size_t Index) {
1082   return previousEqual(Operands, Index, "loop0") ||
1083          previousEqual(Operands, Index, "loop1") ||
1084          previousEqual(Operands, Index, "sp1loop0") ||
1085          previousEqual(Operands, Index, "sp2loop0") ||
1086          previousEqual(Operands, Index, "sp3loop0");
1087 }
1088 }
1089 
splitIdentifier(OperandVector & Operands)1090 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
1091   AsmToken const &Token = getParser().getTok();
1092   StringRef String = Token.getString();
1093   SMLoc Loc = Token.getLoc();
1094   Lex();
1095   do {
1096     std::pair<StringRef, StringRef> HeadTail = String.split('.');
1097     if (!HeadTail.first.empty())
1098       Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));
1099     if (!HeadTail.second.empty())
1100       Operands.push_back(HexagonOperand::CreateToken(
1101           String.substr(HeadTail.first.size(), 1), Loc));
1102     String = HeadTail.second;
1103   } while (!String.empty());
1104   return false;
1105 }
1106 
parseOperand(OperandVector & Operands)1107 bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
1108   unsigned Register;
1109   SMLoc Begin;
1110   SMLoc End;
1111   MCAsmLexer &Lexer = getLexer();
1112   if (!ParseRegister(Register, Begin, End)) {
1113     if (!ErrorMissingParenthesis)
1114       switch (Register) {
1115       default:
1116         break;
1117       case Hexagon::P0:
1118       case Hexagon::P1:
1119       case Hexagon::P2:
1120       case Hexagon::P3:
1121         if (previousEqual(Operands, 0, "if")) {
1122           if (WarnMissingParenthesis)
1123             Warning (Begin, "Missing parenthesis around predicate register");
1124           static char const *LParen = "(";
1125           static char const *RParen = ")";
1126           Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
1127           Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1128           const AsmToken &MaybeDotNew = Lexer.getTok();
1129           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1130               MaybeDotNew.getString().equals_lower(".new"))
1131             splitIdentifier(Operands);
1132           Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1133           return false;
1134         }
1135         if (previousEqual(Operands, 0, "!") &&
1136             previousEqual(Operands, 1, "if")) {
1137           if (WarnMissingParenthesis)
1138             Warning (Begin, "Missing parenthesis around predicate register");
1139           static char const *LParen = "(";
1140           static char const *RParen = ")";
1141           Operands.insert(Operands.end () - 1,
1142                           HexagonOperand::CreateToken(LParen, Begin));
1143           Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1144           const AsmToken &MaybeDotNew = Lexer.getTok();
1145           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1146               MaybeDotNew.getString().equals_lower(".new"))
1147             splitIdentifier(Operands);
1148           Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1149           return false;
1150         }
1151         break;
1152       }
1153     Operands.push_back(HexagonOperand::CreateReg(
1154         Register, Begin, End));
1155     return false;
1156   }
1157   return splitIdentifier(Operands);
1158 }
1159 
isLabel(AsmToken & Token)1160 bool HexagonAsmParser::isLabel(AsmToken &Token) {
1161   MCAsmLexer &Lexer = getLexer();
1162   AsmToken const &Second = Lexer.getTok();
1163   AsmToken Third = Lexer.peekTok();
1164   StringRef String = Token.getString();
1165   if (Token.is(AsmToken::TokenKind::LCurly) ||
1166       Token.is(AsmToken::TokenKind::RCurly))
1167     return false;
1168   if (!Token.is(AsmToken::TokenKind::Identifier))
1169     return true;
1170   if (!matchRegister(String.lower()))
1171     return true;
1172   (void)Second;
1173   assert(Second.is(AsmToken::Colon));
1174   StringRef Raw (String.data(), Third.getString().data() - String.data() +
1175                  Third.getString().size());
1176   std::string Collapsed = Raw;
1177   Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1178                   Collapsed.end());
1179   StringRef Whole = Collapsed;
1180   std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
1181   if (!matchRegister(DotSplit.first.lower()))
1182     return true;
1183   return false;
1184 }
1185 
handleNoncontigiousRegister(bool Contigious,SMLoc & Loc)1186 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {
1187   if (!Contigious && ErrorNoncontigiousRegister) {
1188     Error(Loc, "Register name is not contigious");
1189     return true;
1190   }
1191   if (!Contigious && WarnNoncontigiousRegister)
1192     Warning(Loc, "Register name is not contigious");
1193   return false;
1194 }
1195 
ParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc)1196 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1197   MCAsmLexer &Lexer = getLexer();
1198   StartLoc = getLexer().getLoc();
1199   SmallVector<AsmToken, 5> Lookahead;
1200   StringRef RawString(Lexer.getTok().getString().data(), 0);
1201   bool Again = Lexer.is(AsmToken::Identifier);
1202   bool NeededWorkaround = false;
1203   while (Again) {
1204     AsmToken const &Token = Lexer.getTok();
1205     RawString = StringRef(RawString.data(),
1206                           Token.getString().data() - RawString.data () +
1207                           Token.getString().size());
1208     Lookahead.push_back(Token);
1209     Lexer.Lex();
1210     bool Contigious = Lexer.getTok().getString().data() ==
1211                       Lookahead.back().getString().data() +
1212                       Lookahead.back().getString().size();
1213     bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
1214                 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
1215                 Lexer.is(AsmToken::Colon);
1216     bool Workaround = Lexer.is(AsmToken::Colon) ||
1217                       Lookahead.back().is(AsmToken::Colon);
1218     Again = (Contigious && Type) || (Workaround && Type);
1219     NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
1220   }
1221   std::string Collapsed = RawString;
1222   Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1223                   Collapsed.end());
1224   StringRef FullString = Collapsed;
1225   std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
1226   unsigned DotReg = matchRegister(DotSplit.first.lower());
1227   if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1228     if (DotSplit.second.empty()) {
1229       RegNo = DotReg;
1230       EndLoc = Lexer.getLoc();
1231       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1232         return true;
1233       return false;
1234     } else {
1235       RegNo = DotReg;
1236       size_t First = RawString.find('.');
1237       StringRef DotString (RawString.data() + First, RawString.size() - First);
1238       Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1239       EndLoc = Lexer.getLoc();
1240       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1241         return true;
1242       return false;
1243     }
1244   }
1245   std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1246   unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1247   if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1248     Lexer.UnLex(Lookahead.back());
1249     Lookahead.pop_back();
1250     Lexer.UnLex(Lookahead.back());
1251     Lookahead.pop_back();
1252     RegNo = ColonReg;
1253     EndLoc = Lexer.getLoc();
1254     if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1255       return true;
1256     return false;
1257   }
1258   while (!Lookahead.empty()) {
1259     Lexer.UnLex(Lookahead.back());
1260     Lookahead.pop_back();
1261   }
1262   return true;
1263 }
1264 
implicitExpressionLocation(OperandVector & Operands)1265 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1266   if (previousEqual(Operands, 0, "call"))
1267     return true;
1268   if (previousEqual(Operands, 0, "jump"))
1269     if (!getLexer().getTok().is(AsmToken::Colon))
1270       return true;
1271   if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1272     return true;
1273   if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1274       (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1275     return true;
1276   return false;
1277 }
1278 
parseExpression(MCExpr const * & Expr)1279 bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
1280   llvm::SmallVector<AsmToken, 4> Tokens;
1281   MCAsmLexer &Lexer = getLexer();
1282   bool Done = false;
1283   static char const * Comma = ",";
1284   do {
1285     Tokens.emplace_back (Lexer.getTok());
1286     Lex();
1287     switch (Tokens.back().getKind())
1288     {
1289     case AsmToken::TokenKind::Hash:
1290       if (Tokens.size () > 1)
1291         if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
1292           Tokens.insert(Tokens.end() - 2,
1293                         AsmToken(AsmToken::TokenKind::Comma, Comma));
1294           Done = true;
1295         }
1296       break;
1297     case AsmToken::TokenKind::RCurly:
1298     case AsmToken::TokenKind::EndOfStatement:
1299     case AsmToken::TokenKind::Eof:
1300       Done = true;
1301       break;
1302     default:
1303       break;
1304     }
1305   } while (!Done);
1306   while (!Tokens.empty()) {
1307     Lexer.UnLex(Tokens.back());
1308     Tokens.pop_back();
1309   }
1310   return getParser().parseExpression(Expr);
1311 }
1312 
parseExpressionOrOperand(OperandVector & Operands)1313 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1314   if (implicitExpressionLocation(Operands)) {
1315     MCAsmParser &Parser = getParser();
1316     SMLoc Loc = Parser.getLexer().getLoc();
1317     MCExpr const *Expr = nullptr;
1318     bool Error = parseExpression(Expr);
1319     Expr = HexagonMCExpr::create(Expr, getContext());
1320     if (!Error)
1321       Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc));
1322     return Error;
1323   }
1324   return parseOperand(Operands);
1325 }
1326 
1327 /// Parse an instruction.
parseInstruction(OperandVector & Operands)1328 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1329   MCAsmParser &Parser = getParser();
1330   MCAsmLexer &Lexer = getLexer();
1331   while (true) {
1332     AsmToken const &Token = Parser.getTok();
1333     switch (Token.getKind()) {
1334     case AsmToken::EndOfStatement: {
1335       Lex();
1336       return false;
1337     }
1338     case AsmToken::LCurly: {
1339       if (!Operands.empty())
1340         return true;
1341       Operands.push_back(
1342           HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1343       Lex();
1344       return false;
1345     }
1346     case AsmToken::RCurly: {
1347       if (Operands.empty()) {
1348         Operands.push_back(
1349             HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1350         Lex();
1351       }
1352       return false;
1353     }
1354     case AsmToken::Comma: {
1355       Lex();
1356       continue;
1357     }
1358     case AsmToken::EqualEqual:
1359     case AsmToken::ExclaimEqual:
1360     case AsmToken::GreaterEqual:
1361     case AsmToken::GreaterGreater:
1362     case AsmToken::LessEqual:
1363     case AsmToken::LessLess: {
1364       Operands.push_back(HexagonOperand::CreateToken(
1365           Token.getString().substr(0, 1), Token.getLoc()));
1366       Operands.push_back(HexagonOperand::CreateToken(
1367           Token.getString().substr(1, 1), Token.getLoc()));
1368       Lex();
1369       continue;
1370     }
1371     case AsmToken::Hash: {
1372       bool MustNotExtend = false;
1373       bool ImplicitExpression = implicitExpressionLocation(Operands);
1374       SMLoc ExprLoc = Lexer.getLoc();
1375       if (!ImplicitExpression)
1376         Operands.push_back(
1377           HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1378       Lex();
1379       bool MustExtend = false;
1380       bool HiOnly = false;
1381       bool LoOnly = false;
1382       if (Lexer.is(AsmToken::Hash)) {
1383         Lex();
1384         MustExtend = true;
1385       } else if (ImplicitExpression)
1386         MustNotExtend = true;
1387       AsmToken const &Token = Parser.getTok();
1388       if (Token.is(AsmToken::Identifier)) {
1389         StringRef String = Token.getString();
1390         if (String.lower() == "hi") {
1391           HiOnly = true;
1392         } else if (String.lower() == "lo") {
1393           LoOnly = true;
1394         }
1395         if (HiOnly || LoOnly) {
1396           AsmToken LParen = Lexer.peekTok();
1397           if (!LParen.is(AsmToken::LParen)) {
1398             HiOnly = false;
1399             LoOnly = false;
1400           } else {
1401             Lex();
1402           }
1403         }
1404       }
1405       MCExpr const *Expr = nullptr;
1406       if (parseExpression(Expr))
1407         return true;
1408       int64_t Value;
1409       MCContext &Context = Parser.getContext();
1410       assert(Expr != nullptr);
1411       if (Expr->evaluateAsAbsolute(Value)) {
1412         if (HiOnly)
1413           Expr = MCBinaryExpr::createLShr(
1414               Expr,  MCConstantExpr::create(16, Context), Context);
1415         if (HiOnly || LoOnly)
1416           Expr = MCBinaryExpr::createAnd(Expr,
1417               MCConstantExpr::create(0xffff, Context),
1418                                     Context);
1419       } else {
1420         MCValue Value;
1421         if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
1422           if (!Value.isAbsolute()) {
1423             switch(Value.getAccessVariant()) {
1424             case MCSymbolRefExpr::VariantKind::VK_TPREL:
1425             case MCSymbolRefExpr::VariantKind::VK_DTPREL:
1426               // Don't lazy extend these expression variants
1427               MustNotExtend = !MustExtend;
1428               break;
1429             default:
1430               break;
1431             }
1432           }
1433         }
1434       }
1435       Expr = HexagonMCExpr::create(Expr, Context);
1436       HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
1437       HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
1438       std::unique_ptr<HexagonOperand> Operand =
1439           HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);
1440       Operands.push_back(std::move(Operand));
1441       continue;
1442     }
1443     default:
1444       break;
1445     }
1446     if (parseExpressionOrOperand(Operands))
1447       return true;
1448   }
1449 }
1450 
ParseInstruction(ParseInstructionInfo & Info,StringRef Name,AsmToken ID,OperandVector & Operands)1451 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1452                                         StringRef Name,
1453                                         AsmToken ID,
1454                                         OperandVector &Operands) {
1455   getLexer().UnLex(ID);
1456   return parseInstruction(Operands);
1457 }
1458 
1459 namespace {
makeCombineInst(int opCode,MCOperand & Rdd,MCOperand & MO1,MCOperand & MO2)1460 MCInst makeCombineInst(int opCode, MCOperand &Rdd,
1461                        MCOperand &MO1, MCOperand &MO2) {
1462   MCInst TmpInst;
1463   TmpInst.setOpcode(opCode);
1464   TmpInst.addOperand(Rdd);
1465   TmpInst.addOperand(MO1);
1466   TmpInst.addOperand(MO2);
1467 
1468   return TmpInst;
1469 }
1470 }
1471 
1472 // Define this matcher function after the auto-generated include so we
1473 // have the match class enum definitions.
validateTargetOperandClass(MCParsedAsmOperand & AsmOp,unsigned Kind)1474 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1475                                                       unsigned Kind) {
1476   HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1477 
1478   switch (Kind) {
1479   case MCK_0: {
1480     int64_t Value;
1481     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1482                ? Match_Success
1483                : Match_InvalidOperand;
1484   }
1485   case MCK_1: {
1486     int64_t Value;
1487     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1488                ? Match_Success
1489                : Match_InvalidOperand;
1490   }
1491   case MCK__MINUS_1: {
1492     int64_t Value;
1493     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == -1
1494                ? Match_Success
1495                : Match_InvalidOperand;
1496   }
1497   }
1498   if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1499     StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1500     if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1501       return Match_Success;
1502     if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1503       return Match_Success;
1504   }
1505 
1506   DEBUG(dbgs() << "Unmatched Operand:");
1507   DEBUG(Op->dump());
1508   DEBUG(dbgs() << "\n");
1509 
1510   return Match_InvalidOperand;
1511 }
1512 
OutOfRange(SMLoc IDLoc,long long Val,long long Max)1513 void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1514   std::string errStr;
1515   raw_string_ostream ES(errStr);
1516   ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
1517   if (Max >= 0)
1518     ES << "0-" << Max;
1519   else
1520     ES << Max << "-" << (-Max - 1);
1521   Error(IDLoc, ES.str().c_str());
1522 }
1523 
processInstruction(MCInst & Inst,OperandVector const & Operands,SMLoc IDLoc)1524 int HexagonAsmParser::processInstruction(MCInst &Inst,
1525                                          OperandVector const &Operands,
1526                                          SMLoc IDLoc) {
1527   MCContext &Context = getParser().getContext();
1528   const MCRegisterInfo *RI = getContext().getRegisterInfo();
1529   std::string r = "r";
1530   std::string v = "v";
1531   std::string Colon = ":";
1532 
1533   bool is32bit = false; // used to distinguish between CONST32 and CONST64
1534   switch (Inst.getOpcode()) {
1535   default:
1536     break;
1537 
1538   case Hexagon::A2_iconst: {
1539     Inst.setOpcode(Hexagon::A2_addi);
1540     MCOperand Reg = Inst.getOperand(0);
1541     MCOperand S16 = Inst.getOperand(1);
1542     HexagonMCInstrInfo::setMustNotExtend(*S16.getExpr());
1543     HexagonMCInstrInfo::setS23_2_reloc(*S16.getExpr());
1544     Inst.clear();
1545     Inst.addOperand(Reg);
1546     Inst.addOperand(MCOperand::createReg(Hexagon::R0));
1547     Inst.addOperand(S16);
1548     break;
1549   }
1550   case Hexagon::M4_mpyrr_addr:
1551   case Hexagon::S4_addi_asl_ri:
1552   case Hexagon::S4_addi_lsr_ri:
1553   case Hexagon::S4_andi_asl_ri:
1554   case Hexagon::S4_andi_lsr_ri:
1555   case Hexagon::S4_ori_asl_ri:
1556   case Hexagon::S4_ori_lsr_ri:
1557   case Hexagon::S4_or_andix:
1558   case Hexagon::S4_subi_asl_ri:
1559   case Hexagon::S4_subi_lsr_ri: {
1560     MCOperand &Ry = Inst.getOperand(0);
1561     MCOperand &src = Inst.getOperand(2);
1562     if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1563       return Match_InvalidOperand;
1564     break;
1565   }
1566 
1567   case Hexagon::C2_cmpgei: {
1568     MCOperand &MO = Inst.getOperand(2);
1569     MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1570         MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1571     Inst.setOpcode(Hexagon::C2_cmpgti);
1572     break;
1573   }
1574 
1575   case Hexagon::C2_cmpgeui: {
1576     MCOperand &MO = Inst.getOperand(2);
1577     int64_t Value;
1578     bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1579     (void)Success;
1580     assert(Success && "Assured by matcher");
1581     if (Value == 0) {
1582       MCInst TmpInst;
1583       MCOperand &Pd = Inst.getOperand(0);
1584       MCOperand &Rt = Inst.getOperand(1);
1585       TmpInst.setOpcode(Hexagon::C2_cmpeq);
1586       TmpInst.addOperand(Pd);
1587       TmpInst.addOperand(Rt);
1588       TmpInst.addOperand(Rt);
1589       Inst = TmpInst;
1590     } else {
1591       MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1592           MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1593       Inst.setOpcode(Hexagon::C2_cmpgtui);
1594     }
1595     break;
1596   }
1597 
1598   // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1599   case Hexagon::A2_tfrp: {
1600     MCOperand &MO = Inst.getOperand(1);
1601     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1602     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1603     StringRef Reg1(R1);
1604     MO.setReg(matchRegister(Reg1));
1605     // Add a new operand for the second register in the pair.
1606     std::string R2 = r + llvm::utostr(RegPairNum);
1607     StringRef Reg2(R2);
1608     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1609     Inst.setOpcode(Hexagon::A2_combinew);
1610     break;
1611   }
1612 
1613   case Hexagon::A2_tfrpt:
1614   case Hexagon::A2_tfrpf: {
1615     MCOperand &MO = Inst.getOperand(2);
1616     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1617     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1618     StringRef Reg1(R1);
1619     MO.setReg(matchRegister(Reg1));
1620     // Add a new operand for the second register in the pair.
1621     std::string R2 = r + llvm::utostr(RegPairNum);
1622     StringRef Reg2(R2);
1623     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1624     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1625                        ? Hexagon::C2_ccombinewt
1626                        : Hexagon::C2_ccombinewf);
1627     break;
1628   }
1629   case Hexagon::A2_tfrptnew:
1630   case Hexagon::A2_tfrpfnew: {
1631     MCOperand &MO = Inst.getOperand(2);
1632     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1633     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1634     StringRef Reg1(R1);
1635     MO.setReg(matchRegister(Reg1));
1636     // Add a new operand for the second register in the pair.
1637     std::string R2 = r + llvm::utostr(RegPairNum);
1638     StringRef Reg2(R2);
1639     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1640     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1641                        ? Hexagon::C2_ccombinewnewt
1642                        : Hexagon::C2_ccombinewnewf);
1643     break;
1644   }
1645 
1646   // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
1647   case Hexagon::HEXAGON_V6_vassignpair: {
1648     MCOperand &MO = Inst.getOperand(1);
1649     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1650     std::string R1 = v + llvm::utostr(RegPairNum + 1);
1651     MO.setReg(MatchRegisterName(R1));
1652     // Add a new operand for the second register in the pair.
1653     std::string R2 = v + llvm::utostr(RegPairNum);
1654     Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2)));
1655     Inst.setOpcode(Hexagon::V6_vcombine);
1656     break;
1657   }
1658 
1659   // Translate a "$Rx =  CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1660   case Hexagon::CONST32:
1661   case Hexagon::CONST32_Float_Real:
1662   case Hexagon::CONST32_Int_Real:
1663   case Hexagon::FCONST32_nsdata:
1664     is32bit = true;
1665   // Translate a "$Rx:y =  CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1666   case Hexagon::CONST64_Float_Real:
1667   case Hexagon::CONST64_Int_Real:
1668 
1669     // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1670     if (!Parser.getStreamer().hasRawTextSupport()) {
1671       MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1672       MCOperand &MO_1 = Inst.getOperand(1);
1673       MCOperand &MO_0 = Inst.getOperand(0);
1674 
1675       // push section onto section stack
1676       MES->PushSection();
1677 
1678       std::string myCharStr;
1679       MCSectionELF *mySection;
1680 
1681       // check if this as an immediate or a symbol
1682       int64_t Value;
1683       bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1684       if (Absolute) {
1685         // Create a new section - one for each constant
1686         // Some or all of the zeros are replaced with the given immediate.
1687         if (is32bit) {
1688           std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1689           myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1690                           .drop_back(myImmStr.size())
1691                           .str() +
1692                       myImmStr;
1693         } else {
1694           std::string myImmStr = utohexstr(Value);
1695           myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1696                           .drop_back(myImmStr.size())
1697                           .str() +
1698                       myImmStr;
1699         }
1700 
1701         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1702                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1703       } else if (MO_1.isExpr()) {
1704         // .lita - for expressions
1705         myCharStr = ".lita";
1706         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1707                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1708       } else
1709         llvm_unreachable("unexpected type of machine operand!");
1710 
1711       MES->SwitchSection(mySection);
1712       unsigned byteSize = is32bit ? 4 : 8;
1713       getStreamer().EmitCodeAlignment(byteSize, byteSize);
1714 
1715       MCSymbol *Sym;
1716 
1717       // for symbols, get rid of prepended ".gnu.linkonce.lx."
1718 
1719       // emit symbol if needed
1720       if (Absolute) {
1721         Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1722         if (Sym->isUndefined()) {
1723           getStreamer().EmitLabel(Sym);
1724           getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
1725           getStreamer().EmitIntValue(Value, byteSize);
1726         }
1727       } else if (MO_1.isExpr()) {
1728         const char *StringStart = 0;
1729         const char *StringEnd = 0;
1730         if (*Operands[4]->getStartLoc().getPointer() == '#') {
1731           StringStart = Operands[5]->getStartLoc().getPointer();
1732           StringEnd = Operands[6]->getStartLoc().getPointer();
1733         } else { // no pound
1734           StringStart = Operands[4]->getStartLoc().getPointer();
1735           StringEnd = Operands[5]->getStartLoc().getPointer();
1736         }
1737 
1738         unsigned size = StringEnd - StringStart;
1739         std::string DotConst = ".CONST_";
1740         Sym = getContext().getOrCreateSymbol(DotConst +
1741                                              StringRef(StringStart, size));
1742 
1743         if (Sym->isUndefined()) {
1744           // case where symbol is not yet defined: emit symbol
1745           getStreamer().EmitLabel(Sym);
1746           getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);
1747           getStreamer().EmitValue(MO_1.getExpr(), 4);
1748         }
1749       } else
1750         llvm_unreachable("unexpected type of machine operand!");
1751 
1752       MES->PopSection();
1753 
1754       if (Sym) {
1755         MCInst TmpInst;
1756         if (is32bit) // 32 bit
1757           TmpInst.setOpcode(Hexagon::L2_loadrigp);
1758         else // 64 bit
1759           TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1760 
1761         TmpInst.addOperand(MO_0);
1762         TmpInst.addOperand(
1763             MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));
1764         Inst = TmpInst;
1765       }
1766     }
1767     break;
1768 
1769   // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1770   case Hexagon::A2_tfrpi: {
1771     MCOperand &Rdd = Inst.getOperand(0);
1772     MCOperand &MO = Inst.getOperand(1);
1773     int64_t Value;
1774     int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1775     MCOperand imm(MCOperand::createExpr(
1776         HexagonMCExpr::create(MCConstantExpr::create(sVal, Context), Context)));
1777     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1778     break;
1779   }
1780 
1781   // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1782   case Hexagon::TFRI64_V4: {
1783     MCOperand &Rdd = Inst.getOperand(0);
1784     MCOperand &MO = Inst.getOperand(1);
1785     int64_t Value;
1786     if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1787       int s8 = Hi_32(Value);
1788       if (!isInt<8>(s8))
1789         OutOfRange(IDLoc, s8, -128);
1790       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1791           MCConstantExpr::create(s8, Context), Context))); // upper 32
1792       auto Expr = HexagonMCExpr::create(
1793           MCConstantExpr::create(Lo_32(Value), Context), Context);
1794       HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
1795       MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
1796       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1797     } else {
1798       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1799           MCConstantExpr::create(0, Context), Context))); // upper 32
1800       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1801     }
1802     break;
1803   }
1804 
1805   // Handle $Rdd = combine(##imm, #imm)"
1806   case Hexagon::TFRI64_V2_ext: {
1807     MCOperand &Rdd = Inst.getOperand(0);
1808     MCOperand &MO1 = Inst.getOperand(1);
1809     MCOperand &MO2 = Inst.getOperand(2);
1810     int64_t Value;
1811     if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1812       int s8 = Value;
1813       if (s8 < -128 || s8 > 127)
1814         OutOfRange(IDLoc, s8, -128);
1815     }
1816     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1817     break;
1818   }
1819 
1820   // Handle $Rdd = combine(#imm, ##imm)"
1821   case Hexagon::A4_combineii: {
1822     MCOperand &Rdd = Inst.getOperand(0);
1823     MCOperand &MO1 = Inst.getOperand(1);
1824     int64_t Value;
1825     if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1826       int s8 = Value;
1827       if (s8 < -128 || s8 > 127)
1828         OutOfRange(IDLoc, s8, -128);
1829     }
1830     MCOperand &MO2 = Inst.getOperand(2);
1831     Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1832     break;
1833   }
1834 
1835   case Hexagon::S2_tableidxb_goodsyntax: {
1836     Inst.setOpcode(Hexagon::S2_tableidxb);
1837     break;
1838   }
1839 
1840   case Hexagon::S2_tableidxh_goodsyntax: {
1841     MCInst TmpInst;
1842     MCOperand &Rx = Inst.getOperand(0);
1843     MCOperand &_dst_ = Inst.getOperand(1);
1844     MCOperand &Rs = Inst.getOperand(2);
1845     MCOperand &Imm4 = Inst.getOperand(3);
1846     MCOperand &Imm6 = Inst.getOperand(4);
1847     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1848         Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1849     TmpInst.setOpcode(Hexagon::S2_tableidxh);
1850     TmpInst.addOperand(Rx);
1851     TmpInst.addOperand(_dst_);
1852     TmpInst.addOperand(Rs);
1853     TmpInst.addOperand(Imm4);
1854     TmpInst.addOperand(Imm6);
1855     Inst = TmpInst;
1856     break;
1857   }
1858 
1859   case Hexagon::S2_tableidxw_goodsyntax: {
1860     MCInst TmpInst;
1861     MCOperand &Rx = Inst.getOperand(0);
1862     MCOperand &_dst_ = Inst.getOperand(1);
1863     MCOperand &Rs = Inst.getOperand(2);
1864     MCOperand &Imm4 = Inst.getOperand(3);
1865     MCOperand &Imm6 = Inst.getOperand(4);
1866     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1867         Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context));
1868     TmpInst.setOpcode(Hexagon::S2_tableidxw);
1869     TmpInst.addOperand(Rx);
1870     TmpInst.addOperand(_dst_);
1871     TmpInst.addOperand(Rs);
1872     TmpInst.addOperand(Imm4);
1873     TmpInst.addOperand(Imm6);
1874     Inst = TmpInst;
1875     break;
1876   }
1877 
1878   case Hexagon::S2_tableidxd_goodsyntax: {
1879     MCInst TmpInst;
1880     MCOperand &Rx = Inst.getOperand(0);
1881     MCOperand &_dst_ = Inst.getOperand(1);
1882     MCOperand &Rs = Inst.getOperand(2);
1883     MCOperand &Imm4 = Inst.getOperand(3);
1884     MCOperand &Imm6 = Inst.getOperand(4);
1885     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1886         Imm6.getExpr(), MCConstantExpr::create(3, Context), Context), Context));
1887     TmpInst.setOpcode(Hexagon::S2_tableidxd);
1888     TmpInst.addOperand(Rx);
1889     TmpInst.addOperand(_dst_);
1890     TmpInst.addOperand(Rs);
1891     TmpInst.addOperand(Imm4);
1892     TmpInst.addOperand(Imm6);
1893     Inst = TmpInst;
1894     break;
1895   }
1896 
1897   case Hexagon::M2_mpyui: {
1898     Inst.setOpcode(Hexagon::M2_mpyi);
1899     break;
1900   }
1901   case Hexagon::M2_mpysmi: {
1902     MCInst TmpInst;
1903     MCOperand &Rd = Inst.getOperand(0);
1904     MCOperand &Rs = Inst.getOperand(1);
1905     MCOperand &Imm = Inst.getOperand(2);
1906     int64_t Value;
1907     MCExpr const &Expr = *Imm.getExpr();
1908     bool Absolute = Expr.evaluateAsAbsolute(Value);
1909     assert(Absolute);
1910     (void)Absolute;
1911     if (!HexagonMCInstrInfo::mustExtend(Expr)) {
1912       if (Value < 0 && Value > -256) {
1913         Imm.setExpr(HexagonMCExpr::create(
1914             MCConstantExpr::create(Value * -1, Context), Context));
1915         TmpInst.setOpcode(Hexagon::M2_mpysin);
1916       } else if (Value < 256 && Value >= 0)
1917         TmpInst.setOpcode(Hexagon::M2_mpysip);
1918       else
1919         return Match_InvalidOperand;
1920     } else {
1921       if (Value >= 0)
1922         TmpInst.setOpcode(Hexagon::M2_mpysip);
1923       else
1924         return Match_InvalidOperand;
1925     }
1926     TmpInst.addOperand(Rd);
1927     TmpInst.addOperand(Rs);
1928     TmpInst.addOperand(Imm);
1929     Inst = TmpInst;
1930     break;
1931   }
1932 
1933   case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1934     MCOperand &Imm = Inst.getOperand(2);
1935     MCInst TmpInst;
1936     int64_t Value;
1937     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1938     assert(Absolute);
1939     (void)Absolute;
1940     if (Value == 0) { // convert to $Rd = $Rs
1941       TmpInst.setOpcode(Hexagon::A2_tfr);
1942       MCOperand &Rd = Inst.getOperand(0);
1943       MCOperand &Rs = Inst.getOperand(1);
1944       TmpInst.addOperand(Rd);
1945       TmpInst.addOperand(Rs);
1946     } else {
1947       Imm.setExpr(HexagonMCExpr::create(
1948           MCBinaryExpr::createSub(Imm.getExpr(),
1949                                   MCConstantExpr::create(1, Context), Context),
1950           Context));
1951       TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1952       MCOperand &Rd = Inst.getOperand(0);
1953       MCOperand &Rs = Inst.getOperand(1);
1954       TmpInst.addOperand(Rd);
1955       TmpInst.addOperand(Rs);
1956       TmpInst.addOperand(Imm);
1957     }
1958     Inst = TmpInst;
1959     break;
1960   }
1961 
1962   case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1963     MCOperand &Rdd = Inst.getOperand(0);
1964     MCOperand &Rss = Inst.getOperand(1);
1965     MCOperand &Imm = Inst.getOperand(2);
1966     int64_t Value;
1967     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1968     assert(Absolute);
1969     (void)Absolute;
1970     if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1971       MCInst TmpInst;
1972       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1973       std::string R1 = r + llvm::utostr(RegPairNum + 1);
1974       StringRef Reg1(R1);
1975       Rss.setReg(matchRegister(Reg1));
1976       // Add a new operand for the second register in the pair.
1977       std::string R2 = r + llvm::utostr(RegPairNum);
1978       StringRef Reg2(R2);
1979       TmpInst.setOpcode(Hexagon::A2_combinew);
1980       TmpInst.addOperand(Rdd);
1981       TmpInst.addOperand(Rss);
1982       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1983       Inst = TmpInst;
1984     } else {
1985       Imm.setExpr(HexagonMCExpr::create(
1986           MCBinaryExpr::createSub(Imm.getExpr(),
1987                                   MCConstantExpr::create(1, Context), Context),
1988           Context));
1989       Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1990     }
1991     break;
1992   }
1993 
1994   case Hexagon::A4_boundscheck: {
1995     MCOperand &Rs = Inst.getOperand(1);
1996     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1997     if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1998       Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1999       std::string Name =
2000           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2001       StringRef RegPair = Name;
2002       Rs.setReg(matchRegister(RegPair));
2003     } else { // raw:lo
2004       Inst.setOpcode(Hexagon::A4_boundscheck_lo);
2005       std::string Name =
2006           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2007       StringRef RegPair = Name;
2008       Rs.setReg(matchRegister(RegPair));
2009     }
2010     break;
2011   }
2012 
2013   case Hexagon::A2_addsp: {
2014     MCOperand &Rs = Inst.getOperand(1);
2015     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
2016     if (RegNum & 1) { // Odd mapped to raw:hi
2017       Inst.setOpcode(Hexagon::A2_addsph);
2018       std::string Name =
2019           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2020       StringRef RegPair = Name;
2021       Rs.setReg(matchRegister(RegPair));
2022     } else { // Even mapped raw:lo
2023       Inst.setOpcode(Hexagon::A2_addspl);
2024       std::string Name =
2025           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2026       StringRef RegPair = Name;
2027       Rs.setReg(matchRegister(RegPair));
2028     }
2029     break;
2030   }
2031 
2032   case Hexagon::M2_vrcmpys_s1: {
2033     MCOperand &Rt = Inst.getOperand(2);
2034     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2035     if (RegNum & 1) { // Odd mapped to sat:raw:hi
2036       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
2037       std::string Name =
2038           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2039       StringRef RegPair = Name;
2040       Rt.setReg(matchRegister(RegPair));
2041     } else { // Even mapped sat:raw:lo
2042       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
2043       std::string Name =
2044           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2045       StringRef RegPair = Name;
2046       Rt.setReg(matchRegister(RegPair));
2047     }
2048     break;
2049   }
2050 
2051   case Hexagon::M2_vrcmpys_acc_s1: {
2052     MCInst TmpInst;
2053     MCOperand &Rxx = Inst.getOperand(0);
2054     MCOperand &Rss = Inst.getOperand(2);
2055     MCOperand &Rt = Inst.getOperand(3);
2056     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2057     if (RegNum & 1) { // Odd mapped to sat:raw:hi
2058       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
2059       std::string Name =
2060           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2061       StringRef RegPair = Name;
2062       Rt.setReg(matchRegister(RegPair));
2063     } else { // Even mapped sat:raw:lo
2064       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
2065       std::string Name =
2066           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2067       StringRef RegPair = Name;
2068       Rt.setReg(matchRegister(RegPair));
2069     }
2070     // Registers are in different positions
2071     TmpInst.addOperand(Rxx);
2072     TmpInst.addOperand(Rxx);
2073     TmpInst.addOperand(Rss);
2074     TmpInst.addOperand(Rt);
2075     Inst = TmpInst;
2076     break;
2077   }
2078 
2079   case Hexagon::M2_vrcmpys_s1rp: {
2080     MCOperand &Rt = Inst.getOperand(2);
2081     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2082     if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
2083       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
2084       std::string Name =
2085           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2086       StringRef RegPair = Name;
2087       Rt.setReg(matchRegister(RegPair));
2088     } else { // Even mapped rnd:sat:raw:lo
2089       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
2090       std::string Name =
2091           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2092       StringRef RegPair = Name;
2093       Rt.setReg(matchRegister(RegPair));
2094     }
2095     break;
2096   }
2097 
2098   case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
2099     MCOperand &Imm = Inst.getOperand(2);
2100     int64_t Value;
2101     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2102     assert(Absolute);
2103     (void)Absolute;
2104     if (Value == 0)
2105       Inst.setOpcode(Hexagon::S2_vsathub);
2106     else {
2107       Imm.setExpr(HexagonMCExpr::create(
2108           MCBinaryExpr::createSub(Imm.getExpr(),
2109                                   MCConstantExpr::create(1, Context), Context),
2110           Context));
2111       Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
2112     }
2113     break;
2114   }
2115 
2116   case Hexagon::S5_vasrhrnd_goodsyntax: {
2117     MCOperand &Rdd = Inst.getOperand(0);
2118     MCOperand &Rss = Inst.getOperand(1);
2119     MCOperand &Imm = Inst.getOperand(2);
2120     int64_t Value;
2121     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2122     assert(Absolute);
2123     (void)Absolute;
2124     if (Value == 0) {
2125       MCInst TmpInst;
2126       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
2127       std::string R1 = r + llvm::utostr(RegPairNum + 1);
2128       StringRef Reg1(R1);
2129       Rss.setReg(matchRegister(Reg1));
2130       // Add a new operand for the second register in the pair.
2131       std::string R2 = r + llvm::utostr(RegPairNum);
2132       StringRef Reg2(R2);
2133       TmpInst.setOpcode(Hexagon::A2_combinew);
2134       TmpInst.addOperand(Rdd);
2135       TmpInst.addOperand(Rss);
2136       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
2137       Inst = TmpInst;
2138     } else {
2139       Imm.setExpr(HexagonMCExpr::create(
2140           MCBinaryExpr::createSub(Imm.getExpr(),
2141                                   MCConstantExpr::create(1, Context), Context),
2142           Context));
2143       Inst.setOpcode(Hexagon::S5_vasrhrnd);
2144     }
2145     break;
2146   }
2147 
2148   case Hexagon::A2_not: {
2149     MCInst TmpInst;
2150     MCOperand &Rd = Inst.getOperand(0);
2151     MCOperand &Rs = Inst.getOperand(1);
2152     TmpInst.setOpcode(Hexagon::A2_subri);
2153     TmpInst.addOperand(Rd);
2154     TmpInst.addOperand(MCOperand::createExpr(
2155         HexagonMCExpr::create(MCConstantExpr::create(-1, Context), Context)));
2156     TmpInst.addOperand(Rs);
2157     Inst = TmpInst;
2158     break;
2159   }
2160   } // switch
2161 
2162   return Match_Success;
2163 }
2164 
2165 
matchRegister(StringRef Name)2166 unsigned HexagonAsmParser::matchRegister(StringRef Name) {
2167   if (unsigned Reg = MatchRegisterName(Name))
2168     return Reg;
2169   return MatchRegisterAltName(Name);
2170 }
2171