99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,  in EmitR()  function in art::mips64::Mips64Assembler
304   EmitR(0, rs, rt, rd, 0, 0x21);  in Addu()
312   EmitR(0, rs, rt, rd, 0, 0x2d);  in Daddu()
320   EmitR(0, rs, rt, rd, 0, 0x23);  in Subu()
324   EmitR(0, rs, rt, rd, 0, 0x2f);  in Dsubu()
328   EmitR(0, rs, rt, rd, 2, 0x18);  in MulR6()
332   EmitR(0, rs, rt, rd, 3, 0x18);  in MuhR6()
336   EmitR(0, rs, rt, rd, 2, 0x1a);  in DivR6()
340   EmitR(0, rs, rt, rd, 3, 0x1a);  in ModR6()
344   EmitR(0, rs, rt, rd, 2, 0x1b);  in DivuR6()
348   EmitR(0, rs, rt, rd, 3, 0x1b);  in ModuR6()
352   EmitR(0, rs, rt, rd, 2, 0x1c);  in Dmul()
356   EmitR(0, rs, rt, rd, 3, 0x1c);  in Dmuh()
360   EmitR(0, rs, rt, rd, 2, 0x1e);  in Ddiv()
364   EmitR(0, rs, rt, rd, 3, 0x1e);  in Dmod()
368   EmitR(0, rs, rt, rd, 2, 0x1f);  in Ddivu()
372   EmitR(0, rs, rt, rd, 3, 0x1f);  in Dmodu()
376   EmitR(0, rs, rt, rd, 0, 0x24);  in And()
384   EmitR(0, rs, rt, rd, 0, 0x25);  in Or()
392   EmitR(0, rs, rt, rd, 0, 0x26);  in Xor()
400   EmitR(0, rs, rt, rd, 0, 0x27);  in Nor()
412   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20);  in Seb()
416   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20);  in Seh()
430   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size - 1), pos, 0x3);  in Dext()
437   EmitR(0x1f, rt, rd, static_cast<GpuRegister>(pos + size - 1), pos, 0x04);  in Ins()
444   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos, 0x5);  in Dinsm()
451   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos - 32, 0x6);  in Dinsu()
458   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 1), pos, 0x7);  in Dins()
474   EmitR(0x0, rs, rt, rd, sa, 0x05);  in Lsa()
480   EmitR(0x0, rs, rt, rd, sa, 0x15);  in Dlsa()
508   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);  in Sll()
512   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);  in Srl()
516   EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x02);  in Rotr()
520   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);  in Sra()
524   EmitR(0, rs, rt, rd, 0, 0x04);  in Sllv()
528   EmitR(0, rs, rt, rd, 1, 0x06);  in Rotrv()
532   EmitR(0, rs, rt, rd, 0, 0x06);  in Srlv()
536   EmitR(0, rs, rt, rd, 0, 0x07);  in Srav()
540   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38);  in Dsll()
544   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);  in Dsrl()
548   EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3a);  in Drotr()
552   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);  in Dsra()
556   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c);  in Dsll32()
560   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);  in Dsrl32()
564   EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3e);  in Drotr32()
568   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);  in Dsra32()
572   EmitR(0, rs, rt, rd, 0, 0x14);  in Dsllv()
576   EmitR(0, rs, rt, rd, 0, 0x16);  in Dsrlv()
580   EmitR(0, rs, rt, rd, 1, 0x16);  in Drotrv()
584   EmitR(0, rs, rt, rd, 0, 0x17);  in Dsrav()
652   EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),  in Sync()
673   EmitR(0, rs, rt, rd, 0, 0x2a);  in Slt()
677   EmitR(0, rs, rt, rd, 0, 0x2b);  in Sltu()
689   EmitR(0, rs, rt, rd, 0, 0x35);  in Seleqz()
693   EmitR(0, rs, rt, rd, 0, 0x37);  in Selnez()
713   EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);  in Jalr()
1306   EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),  in Break()
1311   EmitR(0x0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0),  in Nop()