Lines Matching refs:w2
451 GET_VREG w2, w1 // x2<- fp[B]
454 SET_VREG_OBJECT w2, w0 // fp[A]<- x2
456 SET_VREG w2, w0 // fp[A]<- x2
469 GET_VREG w2, w1 // r2<- fp[BBBB]
472 SET_VREG_OBJECT w2, w0 // fp[AA]<- r2
474 SET_VREG w2, w0 // fp[AA]<- r2
487 GET_VREG w2, w1 // w2<- fp[BBBB]
490 SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2
492 SET_VREG w2, w0 // fp[AAAA]<- w2
503 ubfx w2, wINST, #8, #4 // w2<- A
507 SET_VREG_WIDE x3, w2
517 lsr w2, wINST, #8 // w2<- AA
521 SET_VREG_WIDE x3, w2
531 FETCH w2, 1 // w2<- AAAA
534 SET_VREG_WIDE x3, w2
548 GET_VREG w2, w1 // x2<- fp[B]
551 SET_VREG_OBJECT w2, w0 // fp[A]<- x2
553 SET_VREG w2, w0 // fp[A]<- x2
568 GET_VREG w2, w1 // r2<- fp[BBBB]
571 SET_VREG_OBJECT w2, w0 // fp[AA]<- r2
573 SET_VREG w2, w0 // fp[AA]<- r2
588 GET_VREG w2, w1 // w2<- fp[BBBB]
591 SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2
593 SET_VREG w2, w0 // fp[AAAA]<- w2
604 lsr w2, wINST, #8 // r2<- AA
610 SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0
612 SET_VREG w0, w2 // fp[AA]<- r0
622 lsr w2, wINST, #8 // r2<- AA
637 lsr w2, wINST, #8 // r2<- AA
643 SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0
645 SET_VREG w0, w2 // fp[AA]<- r0
655 lsr w2, wINST, #8 // w2<- AA
659 SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj
698 lsr w2, wINST, #8 // r2<- AA
699 GET_VREG w0, w2 // r0<- vAA
721 lsr w2, wINST, #8 // w2<- AA
722 GET_VREG_WIDE x0, w2 // x0<- vAA
746 lsr w2, wINST, #8 // r2<- AA
747 GET_VREG w0, w2 // r0<- vAA
838 FETCH w2, 3 // w2<- hhhh (high middle)
892 FETCH w2, 2 // w2<- BBBB (high
894 orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb
936 lsr w2, wINST, #8 // w2<- AA
937 GET_VREG w0, w2 // w0<- vAA (object)
958 lsr w2, wINST, #8 // w2<- AA
959 GET_VREG w0, w2 // w0<- vAA (object)
1007 ubfx w2, wINST, #8, #4 // w2<- A
1011 SET_VREG w0, w2 // vA<- w0
1023 ubfx w2, wINST, #8, #4 // w2<- A
1029 SET_VREG w3, w2 // vB<- length
1043 mov w2, wINST
1065 mov w2, wINST
1146 lsr w2, wINST, #8 // r2<- AA
1147 GET_VREG w1, w2 // r1<- vAA (exception object)
1263 and w2, w0, #255 // w2<- BB
1265 GET_VREG s1, w2
1288 and w2, w0, #255 // w2<- BB
1290 GET_VREG s1, w2
1313 and w2, w0, #255 // w2<- BB
1315 GET_VREG_WIDE d1, w2
1338 and w2, w0, #255 // w2<- BB
1340 GET_VREG_WIDE d1, w2
1357 and w2, w0, #255 // w2<- BB
1359 GET_VREG_WIDE x1, w2
1384 GET_VREG w2, w0 // w2<- vA
1386 cmp w2, w3 // compare (vA, vB)
1410 GET_VREG w2, w0 // w2<- vA
1412 cmp w2, w3 // compare (vA, vB)
1436 GET_VREG w2, w0 // w2<- vA
1438 cmp w2, w3 // compare (vA, vB)
1462 GET_VREG w2, w0 // w2<- vA
1464 cmp w2, w3 // compare (vA, vB)
1488 GET_VREG w2, w0 // w2<- vA
1490 cmp w2, w3 // compare (vA, vB)
1514 GET_VREG w2, w0 // w2<- vA
1516 cmp w2, w3 // compare (vA, vB)
1538 GET_VREG w2, w0 // w2<- vAA
1541 cmp w2, #0 // compare (vA, 0)
1543 cbz w2, MterpCommonTakenBranchNoFlags
1564 GET_VREG w2, w0 // w2<- vAA
1567 cmp w2, #0 // compare (vA, 0)
1569 cbnz w2, MterpCommonTakenBranchNoFlags
1590 GET_VREG w2, w0 // w2<- vAA
1593 cmp w2, #0 // compare (vA, 0)
1595 tbnz w2, #31, MterpCommonTakenBranchNoFlags
1616 GET_VREG w2, w0 // w2<- vAA
1619 cmp w2, #0 // compare (vA, 0)
1621 tbz w2, #31, MterpCommonTakenBranchNoFlags
1642 GET_VREG w2, w0 // w2<- vAA
1645 cmp w2, #0 // compare (vA, 0)
1668 GET_VREG w2, w0 // w2<- vAA
1671 cmp w2, #0 // compare (vA, 0)
1763 FETCH_B w2, 1, 0 // w2<- BB
1766 GET_VREG w0, w2 // w0<- vBB (array object)
1774 ldr w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
1776 SET_VREG w2, w9 // vAA<- w2
1790 and w2, w0, #255 // w2<- BB
1792 GET_VREG w0, w2 // w0<- vBB (array object)
1815 FETCH_B w2, 1, 0 // w2<- BB
1818 GET_VREG w0, w2 // w0<- vBB (array object)
1822 lsr w2, wINST, #8 // w9<- AA
1825 SET_VREG_OBJECT w0, w2
1847 FETCH_B w2, 1, 0 // w2<- BB
1850 GET_VREG w0, w2 // w0<- vBB (array object)
1858 ldrb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
1860 SET_VREG w2, w9 // vAA<- w2
1881 FETCH_B w2, 1, 0 // w2<- BB
1884 GET_VREG w0, w2 // w0<- vBB (array object)
1892 ldrsb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
1894 SET_VREG w2, w9 // vAA<- w2
1915 FETCH_B w2, 1, 0 // w2<- BB
1918 GET_VREG w0, w2 // w0<- vBB (array object)
1926 ldrh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
1928 SET_VREG w2, w9 // vAA<- w2
1949 FETCH_B w2, 1, 0 // w2<- BB
1952 GET_VREG w0, w2 // w0<- vBB (array object)
1960 ldrsh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC]
1962 SET_VREG w2, w9 // vAA<- w2
1982 FETCH_B w2, 1, 0 // w2<- BB
1985 GET_VREG w0, w2 // w0<- vBB (array object)
1993 GET_VREG w2, w9 // w2<- vAA
1995 str w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
2009 and w2, w0, #255 // w2<- BB
2011 GET_VREG w0, w2 // w0<- vBB (array object)
2035 mov w2, wINST
2059 FETCH_B w2, 1, 0 // w2<- BB
2062 GET_VREG w0, w2 // w0<- vBB (array object)
2070 GET_VREG w2, w9 // w2<- vAA
2072 strb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
2093 FETCH_B w2, 1, 0 // w2<- BB
2096 GET_VREG w0, w2 // w0<- vBB (array object)
2104 GET_VREG w2, w9 // w2<- vAA
2106 strb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
2127 FETCH_B w2, 1, 0 // w2<- BB
2130 GET_VREG w0, w2 // w0<- vBB (array object)
2138 GET_VREG w2, w9 // w2<- vAA
2140 strh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
2161 FETCH_B w2, 1, 0 // w2<- BB
2164 GET_VREG w0, w2 // w0<- vBB (array object)
2172 GET_VREG w2, w9 // w2<- vAA
2174 strh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2
2196 ubfx w2, wINST, #8, #4 // w2<- A
2200 SET_VREG_OBJECT w0, w2 // fp[A]<- w0
2202 SET_VREG w0, w2 // fp[A]<- w0
2225 ubfx w2, wINST, #8, #4 // w2<- A
2229 SET_VREG_WIDE x0, w2
2253 ubfx w2, wINST, #8, #4 // w2<- A
2257 SET_VREG_OBJECT w0, w2 // fp[A]<- w0
2259 SET_VREG w0, w2 // fp[A]<- w0
2285 ubfx w2, wINST, #8, #4 // w2<- A
2289 SET_VREG_OBJECT w0, w2 // fp[A]<- w0
2291 SET_VREG w0, w2 // fp[A]<- w0
2317 ubfx w2, wINST, #8, #4 // w2<- A
2321 SET_VREG_OBJECT w0, w2 // fp[A]<- w0
2323 SET_VREG w0, w2 // fp[A]<- w0
2349 ubfx w2, wINST, #8, #4 // w2<- A
2353 SET_VREG_OBJECT w0, w2 // fp[A]<- w0
2355 SET_VREG w0, w2 // fp[A]<- w0
2381 ubfx w2, wINST, #8, #4 // w2<- A
2385 SET_VREG_OBJECT w0, w2 // fp[A]<- w0
2387 SET_VREG w0, w2 // fp[A]<- w0
2409 ubfx w2, wINST, #8, #4 // w2<- A
2410 GET_VREG w2, w2 // w2<- fp[A]
2429 ubfx w2, wINST, #8, #4 // w2<- A
2446 mov w2, wINST
2470 ubfx w2, wINST, #8, #4 // w2<- A
2471 GET_VREG w2, w2 // w2<- fp[A]
2497 ubfx w2, wINST, #8, #4 // w2<- A
2498 GET_VREG w2, w2 // w2<- fp[A]
2524 ubfx w2, wINST, #8, #4 // w2<- A
2525 GET_VREG w2, w2 // w2<- fp[A]
2551 ubfx w2, wINST, #8, #4 // w2<- A
2552 GET_VREG w2, w2 // w2<- fp[A]
2580 lsr w2, wINST, #8 // w2<- AA
2585 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
2587 SET_VREG w0, w2 // fp[AA]<- w0
2636 lsr w2, wINST, #8 // w2<- AA
2641 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
2643 SET_VREG w0, w2 // fp[AA]<- w0
2669 lsr w2, wINST, #8 // w2<- AA
2674 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
2676 SET_VREG w0, w2 // fp[AA]<- w0
2702 lsr w2, wINST, #8 // w2<- AA
2707 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
2709 SET_VREG w0, w2 // fp[AA]<- w0
2735 lsr w2, wINST, #8 // w2<- AA
2740 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
2742 SET_VREG w0, w2 // fp[AA]<- w0
2768 lsr w2, wINST, #8 // w2<- AA
2773 SET_VREG_OBJECT w0, w2 // fp[AA]<- w0
2775 SET_VREG w0, w2 // fp[AA]<- w0
3475 GET_VREG w2, w1 // x2<- fp[B]
3478 SET_VREG_OBJECT w2, w0 // fp[A]<- x2
3480 SET_VREG w2, w0 // fp[A]<- x2
3761 and w2, w0, #255 // w2<- BB
3763 GET_VREG w0, w2 // w0<- vBB
3800 and w2, w0, #255 // w2<- BB
3802 GET_VREG w0, w2 // w0<- vBB
3840 and w2, w0, #255 // w2<- BB
3842 GET_VREG w0, w2 // w0<- vBB
3879 and w2, w0, #255 // w2<- BB
3881 GET_VREG w0, w2 // w0<- vBB
3918 and w2, w0, #255 // w2<- BB
3920 GET_VREG w0, w2 // w0<- vBB
3925 sdiv w2, w0, w1 // optional op; may set condition codes
3926 msub w0, w2, w1, w0 // w0<- op, w0-w3 changed
3957 and w2, w0, #255 // w2<- BB
3959 GET_VREG w0, w2 // w0<- vBB
3996 and w2, w0, #255 // w2<- BB
3998 GET_VREG w0, w2 // w0<- vBB
4035 and w2, w0, #255 // w2<- BB
4037 GET_VREG w0, w2 // w0<- vBB
4074 and w2, w0, #255 // w2<- BB
4076 GET_VREG w0, w2 // w0<- vBB
4113 and w2, w0, #255 // w2<- BB
4115 GET_VREG w0, w2 // w0<- vBB
4152 and w2, w0, #255 // w2<- BB
4154 GET_VREG w0, w2 // w0<- vBB
4187 lsr w2, w0, #8 // w2<- CC
4189 GET_VREG_WIDE x2, w2 // w2<- vCC
4223 lsr w2, w0, #8 // w2<- CC
4225 GET_VREG_WIDE x2, w2 // w2<- vCC
4259 lsr w2, w0, #8 // w2<- CC
4261 GET_VREG_WIDE x2, w2 // w2<- vCC
4295 lsr w2, w0, #8 // w2<- CC
4297 GET_VREG_WIDE x2, w2 // w2<- vCC
4331 lsr w2, w0, #8 // w2<- CC
4333 GET_VREG_WIDE x2, w2 // w2<- vCC
4367 lsr w2, w0, #8 // w2<- CC
4369 GET_VREG_WIDE x2, w2 // w2<- vCC
4403 lsr w2, w0, #8 // w2<- CC
4405 GET_VREG_WIDE x2, w2 // w2<- vCC
4439 lsr w2, w0, #8 // w2<- CC
4441 GET_VREG_WIDE x2, w2 // w2<- vCC
4468 lsr w2, w0, #8 // w2<- CC
4469 GET_VREG w2, w2 // w2<- vCC (shift count)
4493 lsr w2, w0, #8 // w2<- CC
4494 GET_VREG w2, w2 // w2<- vCC (shift count)
4518 lsr w2, w0, #8 // w2<- CC
4519 GET_VREG w2, w2 // w2<- vCC (shift count)
4676 lsr w2, w0, #8 // w2<- CC
4678 GET_VREG_WIDE d2, w2 // w2<- vCC
4712 lsr w2, w0, #8 // w2<- CC
4714 GET_VREG_WIDE d2, w2 // w2<- vCC
4748 lsr w2, w0, #8 // w2<- CC
4750 GET_VREG_WIDE d2, w2 // w2<- vCC
4784 lsr w2, w0, #8 // w2<- CC
4786 GET_VREG_WIDE d2, w2 // w2<- vCC
4806 lsr w2, w0, #8 // w2<- CC
4808 GET_VREG_WIDE d1, w2 // d1<- vCC
4991 sdiv w2, w0, w1 // optional op; may set condition codes
4992 msub w0, w2, w1, w0 // w0<- op, w0-w3 changed
5235 ubfx w2, wINST, #8, #4 // w2<- A
5237 GET_VREG_WIDE x0, w2 // x0<- vA
5245 SET_VREG_WIDE x0, w2 // vAA<- result
5270 ubfx w2, wINST, #8, #4 // w2<- A
5272 GET_VREG_WIDE x0, w2 // x0<- vA
5280 SET_VREG_WIDE x0, w2 // vAA<- result
5305 ubfx w2, wINST, #8, #4 // w2<- A
5307 GET_VREG_WIDE x0, w2 // x0<- vA
5315 SET_VREG_WIDE x0, w2 // vAA<- result
5340 ubfx w2, wINST, #8, #4 // w2<- A
5342 GET_VREG_WIDE x0, w2 // x0<- vA
5350 SET_VREG_WIDE x0, w2 // vAA<- result
5375 ubfx w2, wINST, #8, #4 // w2<- A
5377 GET_VREG_WIDE x0, w2 // x0<- vA
5385 SET_VREG_WIDE x0, w2 // vAA<- result
5410 ubfx w2, wINST, #8, #4 // w2<- A
5412 GET_VREG_WIDE x0, w2 // x0<- vA
5420 SET_VREG_WIDE x0, w2 // vAA<- result
5445 ubfx w2, wINST, #8, #4 // w2<- A
5447 GET_VREG_WIDE x0, w2 // x0<- vA
5455 SET_VREG_WIDE x0, w2 // vAA<- result
5480 ubfx w2, wINST, #8, #4 // w2<- A
5482 GET_VREG_WIDE x0, w2 // x0<- vA
5490 SET_VREG_WIDE x0, w2 // vAA<- result
5505 ubfx w2, wINST, #8, #4 // w2<- A
5507 GET_VREG_WIDE x0, w2 // x0<- vA
5511 SET_VREG_WIDE x0, w2 // vAA<- result
5526 ubfx w2, wINST, #8, #4 // w2<- A
5528 GET_VREG_WIDE x0, w2 // x0<- vA
5532 SET_VREG_WIDE x0, w2 // vAA<- result
5547 ubfx w2, wINST, #8, #4 // w2<- A
5549 GET_VREG_WIDE x0, w2 // x0<- vA
5553 SET_VREG_WIDE x0, w2 // vAA<- result
5690 ubfx w2, wINST, #8, #4 // w2<- A
5692 GET_VREG_WIDE d0, w2 // x0<- vA
5700 SET_VREG_WIDE d0, w2 // vAA<- result
5725 ubfx w2, wINST, #8, #4 // w2<- A
5727 GET_VREG_WIDE d0, w2 // x0<- vA
5735 SET_VREG_WIDE d0, w2 // vAA<- result
5760 ubfx w2, wINST, #8, #4 // w2<- A
5762 GET_VREG_WIDE d0, w2 // x0<- vA
5770 SET_VREG_WIDE d0, w2 // vAA<- result
5795 ubfx w2, wINST, #8, #4 // w2<- A
5797 GET_VREG_WIDE d0, w2 // x0<- vA
5805 SET_VREG_WIDE d0, w2 // vAA<- result
5816 ubfx w2, wINST, #8, #4 // w2<- A
5818 GET_VREG_WIDE d0, w2 // d0<- vA
5820 ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call)
5823 SET_VREG_WIDE d0, w2 // vAA<- result
5846 lsr w2, wINST, #12 // w2<- B
5848 GET_VREG w0, w2 // w0<- vB
5881 lsr w2, wINST, #12 // w2<- B
5883 GET_VREG w0, w2 // w0<- vB
5916 lsr w2, wINST, #12 // w2<- B
5918 GET_VREG w0, w2 // w0<- vB
5950 lsr w2, wINST, #12 // w2<- B
5952 GET_VREG w0, w2 // w0<- vB
5984 lsr w2, wINST, #12 // w2<- B
5986 GET_VREG w0, w2 // w0<- vB
6018 lsr w2, wINST, #12 // w2<- B
6020 GET_VREG w0, w2 // w0<- vB
6052 lsr w2, wINST, #12 // w2<- B
6054 GET_VREG w0, w2 // w0<- vB
6086 lsr w2, wINST, #12 // w2<- B
6088 GET_VREG w0, w2 // w0<- vB
6126 and w2, w3, #255 // w2<- BB
6127 GET_VREG w0, w2 // w0<- vBB
6166 and w2, w3, #255 // w2<- BB
6167 GET_VREG w0, w2 // w0<- vBB
6207 and w2, w3, #255 // w2<- BB
6208 GET_VREG w0, w2 // w0<- vBB
6247 and w2, w3, #255 // w2<- BB
6248 GET_VREG w0, w2 // w0<- vBB
6287 and w2, w3, #255 // w2<- BB
6288 GET_VREG w0, w2 // w0<- vBB
6327 and w2, w3, #255 // w2<- BB
6328 GET_VREG w0, w2 // w0<- vBB
6367 and w2, w3, #255 // w2<- BB
6368 GET_VREG w0, w2 // w0<- vBB
6407 and w2, w3, #255 // w2<- BB
6408 GET_VREG w0, w2 // w0<- vBB
6447 and w2, w3, #255 // w2<- BB
6448 GET_VREG w0, w2 // w0<- vBB
6487 and w2, w3, #255 // w2<- BB
6488 GET_VREG w0, w2 // w0<- vBB
6527 and w2, w3, #255 // w2<- BB
6528 GET_VREG w0, w2 // w0<- vBB
6548 lsr w2, wINST, #12 // w2<- B
6550 GET_VREG w3, w2 // w3<- object we're operating on
6551 ubfx w2, wINST, #8, #4 // w2<- A
6556 SET_VREG w0, w2 // fp[A]<- w0
6565 lsr w2, wINST, #12 // w2<- B
6567 GET_VREG w3, w2 // w3<- object we're operating on
6568 ubfx w2, wINST, #8, #4 // w2<- A
6572 SET_VREG_WIDE x0, w2
6582 lsr w2, wINST, #12 // w2<- B
6585 GET_VREG w0, w2 // w0<- object we're operating on
6588 ubfx w2, wINST, #8, #4 // w2<- A
6591 SET_VREG_OBJECT w0, w2 // fp[A]<- w0
6602 lsr w2, wINST, #12 // w2<- B
6604 GET_VREG w3, w2 // w3<- fp[B], the object pointer
6605 ubfx w2, wINST, #8, #4 // w2<- A
6607 GET_VREG w0, w2 // w0<- fp[A]
6618 lsr w2, wINST, #12 // w2<- B
6620 GET_VREG w2, w2 // w2<- fp[B], the object pointer
6622 cbz w2, common_errNullObject // object was null
6636 mov w2, wINST
6702 lsr w2, wINST, #12 // w2<- B
6704 GET_VREG w3, w2 // w3<- fp[B], the object pointer
6705 ubfx w2, wINST, #8, #4 // w2<- A
6707 GET_VREG w0, w2 // w0<- fp[A]
6721 lsr w2, wINST, #12 // w2<- B
6723 GET_VREG w3, w2 // w3<- fp[B], the object pointer
6724 ubfx w2, wINST, #8, #4 // w2<- A
6726 GET_VREG w0, w2 // w0<- fp[A]
6740 lsr w2, wINST, #12 // w2<- B
6742 GET_VREG w3, w2 // w3<- fp[B], the object pointer
6743 ubfx w2, wINST, #8, #4 // w2<- A
6745 GET_VREG w0, w2 // w0<- fp[A]
6759 lsr w2, wINST, #12 // w2<- B
6761 GET_VREG w3, w2 // w3<- fp[B], the object pointer
6762 ubfx w2, wINST, #8, #4 // w2<- A
6764 GET_VREG w0, w2 // w0<- fp[A]
6778 lsr w2, wINST, #12 // w2<- B
6780 GET_VREG w3, w2 // w3<- object we're operating on
6781 ubfx w2, wINST, #8, #4 // w2<- A
6786 SET_VREG w0, w2 // fp[A]<- w0
6798 lsr w2, wINST, #12 // w2<- B
6800 GET_VREG w3, w2 // w3<- object we're operating on
6801 ubfx w2, wINST, #8, #4 // w2<- A
6806 SET_VREG w0, w2 // fp[A]<- w0
6818 lsr w2, wINST, #12 // w2<- B
6820 GET_VREG w3, w2 // w3<- object we're operating on
6821 ubfx w2, wINST, #8, #4 // w2<- A
6826 SET_VREG w0, w2 // fp[A]<- w0
6838 lsr w2, wINST, #12 // w2<- B
6840 GET_VREG w3, w2 // w3<- object we're operating on
6841 ubfx w2, wINST, #8, #4 // w2<- A
6846 SET_VREG w0, w2 // fp[A]<- w0
7232 add w2, wINST, wINST // w2<- byte offset
7233 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST
7264 add w2, wINST, wINST // w2<- byte offset
7265 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST