Lines Matching refs:Pseudo
1063 // Pseudo-instructions:
1067 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1069 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt…
1073 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1078 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1081 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1091 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1095 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1099 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1102 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1105 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1111 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1114 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1117 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1120 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1123 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1132 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1134 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1141 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1143 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1169 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1172 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1364 def TCRETURNdi :Pseudo< (outs),
1371 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1376 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1404 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1409 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1419 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1494 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1497 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1500 def ATOMIC_LOAD_AND_I8 : Pseudo<
1503 def ATOMIC_LOAD_OR_I8 : Pseudo<
1506 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1509 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1512 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1515 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1518 def ATOMIC_LOAD_AND_I16 : Pseudo<
1521 def ATOMIC_LOAD_OR_I16 : Pseudo<
1524 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1527 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1530 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1533 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1536 def ATOMIC_LOAD_AND_I32 : Pseudo<
1539 def ATOMIC_LOAD_OR_I32 : Pseudo<
1542 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1545 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1549 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1552 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1555 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1559 def ATOMIC_SWAP_I8 : Pseudo<
1562 def ATOMIC_SWAP_I16 : Pseudo<
1565 def ATOMIC_SWAP_I32 : Pseudo<
2306 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2365 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2371 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2409 // Pseudo instruction to perform FADD in round-to-zero mode.
2411 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2745 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2751 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2754 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2761 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2769 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2777 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2784 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2792 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2801 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2808 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2812 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2819 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2825 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
3496 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3499 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3503 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3506 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3707 // Pseudo-instructions for alternate assembly syntax (never used by codegen).