Lines Matching refs:NAN
14 …UN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32,32-NAN
15 …llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
16 …llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6,32R6-NAN
17 …lc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN
18 … %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
19 … %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6,64R6-NAN
114 ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
115 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
116 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
117 ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
127 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
128 ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
129 ; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
133 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
134 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
135 ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
161 ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
162 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
163 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
164 ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
166 ; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
167 ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
168 ; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
172 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
173 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
174 ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
282 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
283 ; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
284 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
285 ; 32R2-NAN: mthc1 $zero, $[[T2]]
286 ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
296 ; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
297 ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
298 ; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
302 ; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
303 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
304 ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
330 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
331 ; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
332 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
333 ; 32R2-NAN: mthc1 $zero, $[[T2]]
334 ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
344 ; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
345 ; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
346 ; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
350 ; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
351 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
352 ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]