1629             HReg vHi, vLo, vec;  in iselIntExpr_R_wrk()  local
1630             iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);  in iselIntExpr_R_wrk()
1636                case Iop_V256to64_0: vec = vLo; off = -16; break;  in iselIntExpr_R_wrk()
1637                case Iop_V256to64_1: vec = vLo; off =  -8; break;  in iselIntExpr_R_wrk()
3293          HReg vHi, vLo;  in iselVecExpr_wrk()  local
3294          iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);  in iselVecExpr_wrk()
3295          return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo;  in iselVecExpr_wrk()
3754       HReg        vLo  = newVRegV(env);  in iselDVecExpr_wrk()  local
3758       addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));  in iselDVecExpr_wrk()
3761       *rLo = vLo;  in iselDVecExpr_wrk()
3767       HReg        vLo  = newVRegV(env);  in iselDVecExpr_wrk()  local
3771       addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));  in iselDVecExpr_wrk()
3774       *rLo = vLo;  in iselDVecExpr_wrk()
3783             HReg vLo = newVRegV(env);  in iselDVecExpr_wrk()  local
3784             addInstr(env, mk_vMOVsd_RR(vHi, vLo));  in iselDVecExpr_wrk()
3786             *rLo = vLo;  in iselDVecExpr_wrk()
4233       HReg        vLo     = newVRegV(env);  in iselDVecExpr_wrk()  local
4249       addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, m16_rsp));  in iselDVecExpr_wrk()
4251       *rLo = vLo;  in iselDVecExpr_wrk()
4409          HReg vHi, vLo;  in iselStmt()  local
4410          iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Store.data);  in iselStmt()
4411          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));  in iselStmt()
4465          HReg vHi, vLo;  in iselStmt()  local
4466          iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Put.data);  in iselStmt()
4470          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));  in iselStmt()