Lines Matching refs:rn
1911 Register rn, in adc() argument
1921 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in adc()
1922 EmitT32_32(0xf1400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc()
1934 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in adc()
1945 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in adc()
1958 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in adc()
1960 EmitT32_32(0xeb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc()
1971 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adc()
1984 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in adc()
1987 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adc()
1993 Delegate(kAdc, &Assembler::adc, cond, size, rd, rn, operand); in adc()
1999 Register rn, in adcs() argument
2009 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in adcs()
2010 EmitT32_32(0xf1500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adcs()
2022 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in adcs()
2033 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in adcs()
2046 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in adcs()
2048 EmitT32_32(0xeb500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adcs()
2059 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adcs()
2072 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in adcs()
2075 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adcs()
2081 Delegate(kAdcs, &Assembler::adcs, cond, size, rd, rn, operand); in adcs()
2087 Register rn, in add() argument
2096 if (!size.IsWide() && rd.IsLow() && rn.Is(pc) && (imm <= 1020) && in add()
2104 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in add()
2106 EmitT32_16(0x1c00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6)); in add()
2111 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in add()
2118 if (!size.IsWide() && rd.IsLow() && rn.Is(sp) && (imm <= 1020) && in add()
2126 if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && (imm <= 508) && in add()
2134 if (!size.IsNarrow() && rn.Is(pc) && (imm <= 4095) && in add()
2142 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) && in add()
2143 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in add()
2144 EmitT32_32(0xf1000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in add()
2152 if (!size.IsNarrow() && (imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) && in add()
2154 EmitT32_32(0xf2000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in add()
2160 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() && in add()
2170 if (!size.IsNarrow() && rn.Is(sp) && (imm <= 4095) && in add()
2180 if (rn.Is(pc) && immediate_a32.IsValid() && cond.IsNotNever()) { in add()
2187 ((rn.GetCode() & 0xd) != 0xd)) { in add()
2189 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in add()
2194 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) { in add()
2206 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in add()
2208 EmitT32_16(0x1800 | rd.GetCode() | (rn.GetCode() << 3) | in add()
2214 if (!size.IsWide() && rd.Is(rn) && !rm.Is(sp) && in add()
2224 if (!size.IsWide() && rd.Is(rm) && rn.Is(sp) && in add()
2233 if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && !rm.Is(sp)) { in add()
2244 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) && in add()
2245 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in add()
2247 EmitT32_32(0xeb000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in add()
2254 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) && in add()
2265 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) { in add()
2268 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in add()
2273 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) { in add()
2289 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in add()
2292 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in add()
2298 Delegate(kAdd, &Assembler::add, cond, size, rd, rn, operand); in add()
2336 Register rn, in adds() argument
2345 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in adds()
2347 EmitT32_16(0x1c00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6)); in adds()
2352 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in adds()
2359 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) && in adds()
2360 !rd.Is(pc) && (!rn.IsPC() || AllowUnpredictable())) { in adds()
2361 EmitT32_32(0xf1100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adds()
2369 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() && in adds()
2381 if (immediate_a32.IsValid() && cond.IsNotNever() && !rn.Is(sp)) { in adds()
2383 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in adds()
2388 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) { in adds()
2400 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in adds()
2402 EmitT32_16(0x1800 | rd.GetCode() | (rn.GetCode() << 3) | in adds()
2413 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) && in adds()
2414 !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in adds()
2416 EmitT32_32(0xeb100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adds()
2423 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) && in adds()
2434 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) { in adds()
2437 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adds()
2442 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) { in adds()
2458 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in adds()
2461 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adds()
2467 Delegate(kAdds, &Assembler::adds, cond, size, rd, rn, operand); in adds()
2489 Register rn, in addw() argument
2497 if (rn.Is(pc) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) { in addw()
2504 if ((imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) && in addw()
2506 EmitT32_32(0xf2000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in addw()
2512 if (rn.Is(sp) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) { in addw()
2520 Delegate(kAddw, &Assembler::addw, cond, rd, rn, operand); in addw()
2683 Register rn, in and_() argument
2693 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in and_()
2694 EmitT32_32(0xf0000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in and_()
2706 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in and_()
2717 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in and_()
2730 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in and_()
2732 EmitT32_32(0xea000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in and_()
2743 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in and_()
2756 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in and_()
2759 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in and_()
2765 Delegate(kAnd, &Assembler::and_, cond, size, rd, rn, operand); in and_()
2771 Register rn, in ands() argument
2781 (!rn.IsPC() || AllowUnpredictable())) { in ands()
2782 EmitT32_32(0xf0100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in ands()
2794 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in ands()
2805 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in ands()
2818 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in ands()
2820 EmitT32_32(0xea100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in ands()
2831 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ands()
2844 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in ands()
2847 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ands()
2853 Delegate(kAnds, &Assembler::ands, cond, size, rd, rn, operand); in ands()
3207 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) { in bfi() argument
3212 if ((lsb <= 31) && !rn.Is(pc) && in bfi()
3216 EmitT32_32(0xf3600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in bfi()
3223 if ((lsb <= 31) && cond.IsNotNever() && !rn.Is(pc) && in bfi()
3228 rn.GetCode() | (lsb << 7) | (msb << 16)); in bfi()
3232 Delegate(kBfi, &Assembler::bfi, cond, rd, rn, lsb, width); in bfi()
3238 Register rn, in bic() argument
3248 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in bic()
3249 EmitT32_32(0xf0200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in bic()
3261 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in bic()
3272 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in bic()
3285 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in bic()
3287 EmitT32_32(0xea200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in bic()
3298 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in bic()
3311 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in bic()
3314 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in bic()
3320 Delegate(kBic, &Assembler::bic, cond, size, rd, rn, operand); in bic()
3326 Register rn, in bics() argument
3336 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in bics()
3337 EmitT32_32(0xf0300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in bics()
3349 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in bics()
3360 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in bics()
3373 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in bics()
3375 EmitT32_32(0xea300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in bics()
3386 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in bics()
3399 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in bics()
3402 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in bics()
3408 Delegate(kBics, &Assembler::bics, cond, size, rd, rn, operand); in bics()
3669 void Assembler::cbnz(Register rn, Location* location) { in cbnz() argument
3679 if (rn.IsLow() && ((location->IsBound() && (offset >= 0) && in cbnz()
3696 EmitT32_16(Link(0xb900 | rn.GetCode(), location, immop, &kT16CbzInfo)); in cbnz()
3701 Delegate(kCbnz, &Assembler::cbnz, rn, location); in cbnz()
3704 bool Assembler::cbnz_info(Register rn, in cbnz_info() argument
3711 if (rn.IsLow()) { in cbnz_info()
3719 void Assembler::cbz(Register rn, Location* location) { in cbz() argument
3729 if (rn.IsLow() && ((location->IsBound() && (offset >= 0) && in cbz()
3746 EmitT32_16(Link(0xb100 | rn.GetCode(), location, immop, &kT16CbzInfo)); in cbz()
3751 Delegate(kCbz, &Assembler::cbz, rn, location); in cbz()
3754 bool Assembler::cbz_info(Register rn, in cbz_info() argument
3761 if (rn.IsLow()) { in cbz_info()
3812 Register rn, in cmn() argument
3822 (!rn.IsPC() || AllowUnpredictable())) { in cmn()
3823 EmitT32_32(0xf1100f00U | (rn.GetCode() << 16) | in cmn()
3835 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue()); in cmn()
3845 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) { in cmn()
3846 EmitT32_16(0x42c0 | rn.GetCode() | (rm.GetCode() << 3)); in cmn()
3857 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in cmn()
3859 EmitT32_32(0xeb100f00U | (rn.GetCode() << 16) | rm.GetCode() | in cmn()
3870 (rn.GetCode() << 16) | rm.GetCode() | in cmn()
3883 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) { in cmn()
3885 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) | in cmn()
3891 Delegate(kCmn, &Assembler::cmn, cond, size, rn, operand); in cmn()
3896 Register rn, in cmp() argument
3905 if (!size.IsWide() && rn.IsLow() && (imm <= 255)) { in cmp()
3906 EmitT32_16(0x2800 | (rn.GetCode() << 8) | imm); in cmp()
3912 (!rn.IsPC() || AllowUnpredictable())) { in cmp()
3913 EmitT32_32(0xf1b00f00U | (rn.GetCode() << 16) | in cmp()
3925 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue()); in cmp()
3935 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) { in cmp()
3936 EmitT32_16(0x4280 | rn.GetCode() | (rm.GetCode() << 3)); in cmp()
3942 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in cmp()
3943 EmitT32_16(0x4500 | (rn.GetCode() & 0x7) | in cmp()
3944 ((rn.GetCode() & 0x8) << 4) | (rm.GetCode() << 3)); in cmp()
3955 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in cmp()
3957 EmitT32_32(0xebb00f00U | (rn.GetCode() << 16) | rm.GetCode() | in cmp()
3968 (rn.GetCode() << 16) | rm.GetCode() | in cmp()
3981 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) { in cmp()
3983 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) | in cmp()
3989 Delegate(kCmp, &Assembler::cmp, cond, size, rn, operand); in cmp()
3992 void Assembler::crc32b(Condition cond, Register rd, Register rn, Register rm) { in crc32b() argument
3997 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) || in crc32b()
3999 EmitT32_32(0xfac0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in crc32b()
4007 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in crc32b()
4009 (rn.GetCode() << 16) | rm.GetCode()); in crc32b()
4013 Delegate(kCrc32b, &Assembler::crc32b, cond, rd, rn, rm); in crc32b()
4016 void Assembler::crc32cb(Condition cond, Register rd, Register rn, Register rm) { in crc32cb() argument
4021 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) || in crc32cb()
4023 EmitT32_32(0xfad0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in crc32cb()
4031 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in crc32cb()
4033 (rn.GetCode() << 16) | rm.GetCode()); in crc32cb()
4037 Delegate(kCrc32cb, &Assembler::crc32cb, cond, rd, rn, rm); in crc32cb()
4040 void Assembler::crc32ch(Condition cond, Register rd, Register rn, Register rm) { in crc32ch() argument
4045 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) || in crc32ch()
4047 EmitT32_32(0xfad0f090U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in crc32ch()
4055 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in crc32ch()
4057 (rn.GetCode() << 16) | rm.GetCode()); in crc32ch()
4061 Delegate(kCrc32ch, &Assembler::crc32ch, cond, rd, rn, rm); in crc32ch()
4064 void Assembler::crc32cw(Condition cond, Register rd, Register rn, Register rm) { in crc32cw() argument
4069 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) || in crc32cw()
4071 EmitT32_32(0xfad0f0a0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in crc32cw()
4079 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in crc32cw()
4081 (rn.GetCode() << 16) | rm.GetCode()); in crc32cw()
4085 Delegate(kCrc32cw, &Assembler::crc32cw, cond, rd, rn, rm); in crc32cw()
4088 void Assembler::crc32h(Condition cond, Register rd, Register rn, Register rm) { in crc32h() argument
4093 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) || in crc32h()
4095 EmitT32_32(0xfac0f090U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in crc32h()
4103 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in crc32h()
4105 (rn.GetCode() << 16) | rm.GetCode()); in crc32h()
4109 Delegate(kCrc32h, &Assembler::crc32h, cond, rd, rn, rm); in crc32h()
4112 void Assembler::crc32w(Condition cond, Register rd, Register rn, Register rm) { in crc32w() argument
4117 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) || in crc32w()
4119 EmitT32_32(0xfac0f0a0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in crc32w()
4127 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in crc32w()
4129 (rn.GetCode() << 16) | rm.GetCode()); in crc32w()
4133 Delegate(kCrc32w, &Assembler::crc32w, cond, rd, rn, rm); in crc32w()
4175 Register rn, in eor() argument
4185 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in eor()
4186 EmitT32_32(0xf0800000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in eor()
4198 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in eor()
4209 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in eor()
4222 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in eor()
4224 EmitT32_32(0xea800000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in eor()
4235 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in eor()
4248 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in eor()
4251 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in eor()
4257 Delegate(kEor, &Assembler::eor, cond, size, rd, rn, operand); in eor()
4263 Register rn, in eors() argument
4273 (!rn.IsPC() || AllowUnpredictable())) { in eors()
4274 EmitT32_32(0xf0900000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in eors()
4286 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in eors()
4297 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in eors()
4310 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in eors()
4312 EmitT32_32(0xea900000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in eors()
4323 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in eors()
4336 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in eors()
4339 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in eors()
4345 Delegate(kEors, &Assembler::eors, cond, size, rd, rn, operand); in eors()
4349 Register rn, in fldmdbx() argument
4358 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) || in fldmdbx()
4362 EmitT32_32(0xed300b01U | (rn.GetCode() << 16) | dreg.Encode(22, 12) | in fldmdbx()
4371 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) || in fldmdbx()
4375 EmitA32(0x0d300b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in fldmdbx()
4380 Delegate(kFldmdbx, &Assembler::fldmdbx, cond, rn, write_back, dreglist); in fldmdbx()
4384 Register rn, in fldmiax() argument
4392 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) || in fldmiax()
4396 EmitT32_32(0xec900b01U | (rn.GetCode() << 16) | in fldmiax()
4406 (!rn.IsPC() || !write_back.DoesWriteBack())) || in fldmiax()
4410 EmitA32(0x0c900b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in fldmiax()
4416 Delegate(kFldmiax, &Assembler::fldmiax, cond, rn, write_back, dreglist); in fldmiax()
4420 Register rn, in fstmdbx() argument
4429 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) || in fstmdbx()
4433 EmitT32_32(0xed200b01U | (rn.GetCode() << 16) | dreg.Encode(22, 12) | in fstmdbx()
4442 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) || in fstmdbx()
4446 EmitA32(0x0d200b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in fstmdbx()
4451 Delegate(kFstmdbx, &Assembler::fstmdbx, cond, rn, write_back, dreglist); in fstmdbx()
4455 Register rn, in fstmiax() argument
4463 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) || in fstmiax()
4467 EmitT32_32(0xec800b01U | (rn.GetCode() << 16) | in fstmiax()
4477 (!rn.IsPC() || !write_back.DoesWriteBack())) || in fstmiax()
4481 EmitA32(0x0c800b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in fstmiax()
4487 Delegate(kFstmiax, &Assembler::fstmiax, cond, rn, write_back, dreglist); in fstmiax()
4574 Register rn = operand.GetBaseRegister(); in lda() local
4578 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in lda()
4579 EmitT32_32(0xe8d00fafU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in lda()
4586 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in lda()
4588 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in lda()
4600 Register rn = operand.GetBaseRegister(); in ldab() local
4604 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldab()
4605 EmitT32_32(0xe8d00f8fU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldab()
4612 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldab()
4614 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldab()
4626 Register rn = operand.GetBaseRegister(); in ldaex() local
4630 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldaex()
4631 EmitT32_32(0xe8d00fefU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldaex()
4638 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldaex()
4640 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldaex()
4652 Register rn = operand.GetBaseRegister(); in ldaexb() local
4656 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldaexb()
4657 EmitT32_32(0xe8d00fcfU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldaexb()
4664 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldaexb()
4666 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldaexb()
4681 Register rn = operand.GetBaseRegister(); in ldaexd() local
4685 ((!rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldaexd()
4687 (rn.GetCode() << 16)); in ldaexd()
4695 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rn.IsPC()) || in ldaexd()
4698 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldaexd()
4710 Register rn = operand.GetBaseRegister(); in ldaexh() local
4714 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldaexh()
4715 EmitT32_32(0xe8d00fdfU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldaexh()
4722 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldaexh()
4724 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldaexh()
4736 Register rn = operand.GetBaseRegister(); in ldah() local
4740 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldah()
4741 EmitT32_32(0xe8d00f9fU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldah()
4748 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldah()
4750 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldah()
4760 Register rn, in ldm() argument
4767 if (!size.IsWide() && rn.IsLow() && in ldm()
4768 (((registers.GetList() & (1 << rn.GetCode())) == 0) == in ldm()
4771 EmitT32_16(0xc800 | (rn.GetCode() << 8) | in ldm()
4777 if (!size.IsWide() && rn.Is(sp) && write_back.DoesWriteBack() && in ldm()
4786 (!rn.IsPC() || AllowUnpredictable())) { in ldm()
4787 EmitT32_32(0xe8900000U | (rn.GetCode() << 16) | in ldm()
4797 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldm()
4798 EmitA32(0x08900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldm()
4804 Delegate(kLdm, &Assembler::ldm, cond, size, rn, write_back, registers); in ldm()
4808 Register rn, in ldmda() argument
4815 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldmda()
4816 EmitA32(0x08100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldmda()
4822 Delegate(kLdmda, &Assembler::ldmda, cond, rn, write_back, registers); in ldmda()
4826 Register rn, in ldmdb() argument
4834 (!rn.IsPC() || AllowUnpredictable())) { in ldmdb()
4835 EmitT32_32(0xe9100000U | (rn.GetCode() << 16) | in ldmdb()
4845 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldmdb()
4846 EmitA32(0x09100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldmdb()
4852 Delegate(kLdmdb, &Assembler::ldmdb, cond, rn, write_back, registers); in ldmdb()
4856 Register rn, in ldmea() argument
4864 (!rn.IsPC() || AllowUnpredictable())) { in ldmea()
4865 EmitT32_32(0xe9100000U | (rn.GetCode() << 16) | in ldmea()
4875 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldmea()
4876 EmitA32(0x09100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldmea()
4882 Delegate(kLdmea, &Assembler::ldmea, cond, rn, write_back, registers); in ldmea()
4886 Register rn, in ldmed() argument
4893 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldmed()
4894 EmitA32(0x09900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldmed()
4900 Delegate(kLdmed, &Assembler::ldmed, cond, rn, write_back, registers); in ldmed()
4904 Register rn, in ldmfa() argument
4911 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldmfa()
4912 EmitA32(0x08100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldmfa()
4918 Delegate(kLdmfa, &Assembler::ldmfa, cond, rn, write_back, registers); in ldmfa()
4923 Register rn, in ldmfd() argument
4930 if (!size.IsWide() && rn.IsLow() && in ldmfd()
4931 (((registers.GetList() & (1 << rn.GetCode())) == 0) == in ldmfd()
4934 EmitT32_16(0xc800 | (rn.GetCode() << 8) | in ldmfd()
4941 (!rn.IsPC() || AllowUnpredictable())) { in ldmfd()
4942 EmitT32_32(0xe8900000U | (rn.GetCode() << 16) | in ldmfd()
4952 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldmfd()
4953 EmitA32(0x08900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldmfd()
4959 Delegate(kLdmfd, &Assembler::ldmfd, cond, size, rn, write_back, registers); in ldmfd()
4963 Register rn, in ldmib() argument
4970 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in ldmib()
4971 EmitA32(0x09900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in ldmib()
4977 Delegate(kLdmib, &Assembler::ldmib, cond, rn, write_back, registers); in ldmib()
4987 Register rn = operand.GetBaseRegister(); in ldr() local
4991 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) && in ldr()
4994 EmitT32_16(0x6800 | rt.GetCode() | (rn.GetCode() << 3) | in ldr()
5001 ((offset % 4) == 0) && rn.Is(sp) && operand.IsOffset()) { in ldr()
5009 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in ldr()
5012 EmitT32_32(0xf8d00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldr()
5019 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in ldr()
5022 EmitT32_32(0xf8500c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldr()
5029 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) && in ldr()
5034 EmitT32_32(0xf8500900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldr()
5041 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) && in ldr()
5046 EmitT32_32(0xf8500d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldr()
5053 rn.Is(pc) && operand.IsOffset() && in ldr()
5065 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf)) { in ldr()
5069 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in ldr()
5075 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf)) { in ldr()
5079 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in ldr()
5085 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf)) { in ldr()
5089 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in ldr()
5094 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) && in ldr()
5105 Register rn = operand.GetBaseRegister(); in ldr() local
5110 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in ldr()
5112 EmitT32_16(0x5800 | rt.GetCode() | (rn.GetCode() << 3) | in ldr()
5120 Register rn = operand.GetBaseRegister(); in ldr() local
5128 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in ldr()
5131 EmitT32_32(0xf8500000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldr()
5144 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldr()
5155 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldr()
5166 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldr()
5303 Register rn = operand.GetBaseRegister(); in ldrb() local
5307 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) && in ldrb()
5309 EmitT32_16(0x7800 | rt.GetCode() | (rn.GetCode() << 3) | in ldrb()
5316 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrb()
5317 EmitT32_32(0xf8900000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrb()
5324 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrb()
5325 EmitT32_32(0xf8100c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrb()
5332 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrb()
5335 EmitT32_32(0xf8100900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrb()
5342 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrb()
5345 EmitT32_32(0xf8100d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrb()
5352 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) { in ldrb()
5362 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrb()
5367 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in ldrb()
5373 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrb()
5378 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in ldrb()
5384 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrb()
5389 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in ldrb()
5394 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) && in ldrb()
5406 Register rn = operand.GetBaseRegister(); in ldrb() local
5411 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in ldrb()
5413 EmitT32_16(0x5c00 | rt.GetCode() | (rn.GetCode() << 3) | in ldrb()
5421 Register rn = operand.GetBaseRegister(); in ldrb() local
5429 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) && in ldrb()
5431 EmitT32_32(0xf8100000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrb()
5444 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrb()
5456 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrb()
5467 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrb()
5569 Register rn = operand.GetBaseRegister(); in ldrd() local
5574 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in ldrd()
5579 (rn.GetCode() << 16) | offset_ | (sign << 23)); in ldrd()
5585 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) && in ldrd()
5590 (rn.GetCode() << 16) | offset_ | (sign << 23)); in ldrd()
5596 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) && in ldrd()
5601 (rn.GetCode() << 16) | offset_ | (sign << 23)); in ldrd()
5606 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) && in ldrd()
5620 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrd()
5626 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrd()
5633 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrd()
5639 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrd()
5646 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrd()
5652 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrd()
5658 (offset >= -255) && (offset <= 255) && rn.Is(pc) && in ldrd()
5672 Register rn = operand.GetBaseRegister(); in ldrd() local
5683 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrd()
5694 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrd()
5705 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrd()
5815 Register rn = operand.GetBaseRegister(); in ldrex() local
5821 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldrex()
5823 EmitT32_32(0xe8500f00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrex()
5831 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldrex()
5833 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldrex()
5845 Register rn = operand.GetBaseRegister(); in ldrexb() local
5849 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldrexb()
5850 EmitT32_32(0xe8d00f4fU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldrexb()
5857 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldrexb()
5859 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldrexb()
5874 Register rn = operand.GetBaseRegister(); in ldrexd() local
5878 ((!rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldrexd()
5880 (rn.GetCode() << 16)); in ldrexd()
5888 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rn.IsPC()) || in ldrexd()
5891 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldrexd()
5903 Register rn = operand.GetBaseRegister(); in ldrexh() local
5907 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldrexh()
5908 EmitT32_32(0xe8d00f5fU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldrexh()
5915 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ldrexh()
5917 (rt.GetCode() << 12) | (rn.GetCode() << 16)); in ldrexh()
5932 Register rn = operand.GetBaseRegister(); in ldrh() local
5936 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) && in ldrh()
5939 EmitT32_16(0x8800 | rt.GetCode() | (rn.GetCode() << 3) | in ldrh()
5946 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrh()
5947 EmitT32_32(0xf8b00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrh()
5954 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrh()
5955 EmitT32_32(0xf8300c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrh()
5962 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrh()
5965 EmitT32_32(0xf8300900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrh()
5972 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrh()
5975 EmitT32_32(0xf8300d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrh()
5982 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) { in ldrh()
5992 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrh()
5997 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrh()
6003 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrh()
6008 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrh()
6014 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrh()
6019 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrh()
6024 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) && in ldrh()
6037 Register rn = operand.GetBaseRegister(); in ldrh() local
6042 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in ldrh()
6044 EmitT32_16(0x5a00 | rt.GetCode() | (rn.GetCode() << 3) | in ldrh()
6055 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrh()
6064 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrh()
6073 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrh()
6080 Register rn = operand.GetBaseRegister(); in ldrh() local
6088 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) && in ldrh()
6090 EmitT32_32(0xf8300000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrh()
6194 Register rn = operand.GetBaseRegister(); in ldrsb() local
6199 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrsb()
6200 EmitT32_32(0xf9900000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsb()
6207 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrsb()
6208 EmitT32_32(0xf9100c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsb()
6215 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrsb()
6218 EmitT32_32(0xf9100900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsb()
6225 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrsb()
6228 EmitT32_32(0xf9100d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsb()
6235 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) { in ldrsb()
6245 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrsb()
6250 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrsb()
6256 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrsb()
6261 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrsb()
6267 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrsb()
6272 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrsb()
6277 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) && in ldrsb()
6290 Register rn = operand.GetBaseRegister(); in ldrsb() local
6295 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in ldrsb()
6297 EmitT32_16(0x5600 | rt.GetCode() | (rn.GetCode() << 3) | in ldrsb()
6308 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrsb()
6317 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrsb()
6326 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrsb()
6333 Register rn = operand.GetBaseRegister(); in ldrsb() local
6341 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) && in ldrsb()
6343 EmitT32_32(0xf9100000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsb()
6447 Register rn = operand.GetBaseRegister(); in ldrsh() local
6452 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrsh()
6453 EmitT32_32(0xf9b00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsh()
6460 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) { in ldrsh()
6461 EmitT32_32(0xf9300c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsh()
6468 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrsh()
6471 EmitT32_32(0xf9300900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsh()
6478 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) { in ldrsh()
6481 EmitT32_32(0xf9300d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsh()
6488 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) { in ldrsh()
6498 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrsh()
6503 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrsh()
6509 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrsh()
6514 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrsh()
6520 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) && in ldrsh()
6525 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in ldrsh()
6530 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) && in ldrsh()
6543 Register rn = operand.GetBaseRegister(); in ldrsh() local
6548 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in ldrsh()
6550 EmitT32_16(0x5e00 | rt.GetCode() | (rn.GetCode() << 3) | in ldrsh()
6561 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrsh()
6570 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrsh()
6579 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in ldrsh()
6586 Register rn = operand.GetBaseRegister(); in ldrsh() local
6594 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) && in ldrsh()
6596 EmitT32_32(0xf9300000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in ldrsh()
6962 Condition cond, Register rd, Register rn, Register rm, Register ra) { in mla() argument
6968 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in mla()
6969 EmitT32_32(0xfb000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in mla()
6977 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in mla()
6980 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in mla()
6984 Delegate(kMla, &Assembler::mla, cond, rd, rn, rm, ra); in mla()
6988 Condition cond, Register rd, Register rn, Register rm, Register ra) { in mlas() argument
6994 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in mlas()
6997 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in mlas()
7001 Delegate(kMlas, &Assembler::mlas, cond, rd, rn, rm, ra); in mlas()
7005 Condition cond, Register rd, Register rn, Register rm, Register ra) { in mls() argument
7010 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in mls()
7012 EmitT32_32(0xfb000010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in mls()
7020 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in mls()
7023 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in mls()
7027 Delegate(kMls, &Assembler::mls, cond, rd, rn, rm, ra); in mls()
7410 Register rn = operand.GetBaseRegister(); in msr() local
7413 if ((!rn.IsPC() || AllowUnpredictable())) { in msr()
7415 ((spec_reg.GetReg() & 0x10) << 16) | (rn.GetCode() << 16)); in msr()
7421 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in msr()
7424 ((spec_reg.GetReg() & 0x10) << 18) | rn.GetCode()); in msr()
7433 Condition cond, EncodingSize size, Register rd, Register rn, Register rm) { in mul() argument
7438 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rn.IsLow() && in mul()
7440 EmitT32_16(0x4340 | rd.GetCode() | (rn.GetCode() << 3)); in mul()
7446 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in mul()
7447 EmitT32_32(0xfb00f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in mul()
7455 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in mul()
7457 rn.GetCode() | (rm.GetCode() << 8)); in mul()
7461 Delegate(kMul, &Assembler::mul, cond, size, rd, rn, rm); in mul()
7464 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) { in muls() argument
7469 if (OutsideITBlock() && rd.Is(rm) && rn.IsLow() && rm.IsLow()) { in muls()
7470 EmitT32_16(0x4340 | rd.GetCode() | (rn.GetCode() << 3)); in muls()
7477 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in muls()
7479 rn.GetCode() | (rm.GetCode() << 8)); in muls()
7483 Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm); in muls()
7682 Register rn, in orn() argument
7691 if (immediate_t32.IsValid() && !rn.Is(pc) && in orn()
7693 EmitT32_32(0xf0600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orn()
7708 if (shift.IsValidAmount(amount) && !rn.Is(pc) && in orn()
7711 EmitT32_32(0xea600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orn()
7719 Delegate(kOrn, &Assembler::orn, cond, rd, rn, operand); in orn()
7724 Register rn, in orns() argument
7733 if (immediate_t32.IsValid() && !rn.Is(pc) && in orns()
7735 EmitT32_32(0xf0700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orns()
7750 if (shift.IsValidAmount(amount) && !rn.Is(pc) && in orns()
7753 EmitT32_32(0xea700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orns()
7761 Delegate(kOrns, &Assembler::orns, cond, rd, rn, operand); in orns()
7767 Register rn, in orr() argument
7776 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(pc) && in orr()
7778 EmitT32_32(0xf0400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orr()
7790 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in orr()
7801 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in orr()
7813 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(pc) && in orr()
7816 EmitT32_32(0xea400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orr()
7827 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in orr()
7840 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in orr()
7843 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in orr()
7849 Delegate(kOrr, &Assembler::orr, cond, size, rd, rn, operand); in orr()
7855 Register rn, in orrs() argument
7864 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(pc) && in orrs()
7866 EmitT32_32(0xf0500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orrs()
7878 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in orrs()
7889 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in orrs()
7901 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(pc) && in orrs()
7904 EmitT32_32(0xea500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in orrs()
7915 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in orrs()
7928 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in orrs()
7931 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in orrs()
7937 Delegate(kOrrs, &Assembler::orrs, cond, size, rd, rn, operand); in orrs()
7942 Register rn, in pkhbt() argument
7953 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in pkhbt()
7954 EmitT32_32(0xeac00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in pkhbt()
7963 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in pkhbt()
7965 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in pkhbt()
7971 Delegate(kPkhbt, &Assembler::pkhbt, cond, rd, rn, operand); in pkhbt()
7976 Register rn, in pkhtb() argument
7987 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in pkhtb()
7989 EmitT32_32(0xeac00020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in pkhtb()
7999 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in pkhtb()
8002 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in pkhtb()
8008 Delegate(kPkhtb, &Assembler::pkhtb, cond, rd, rn, operand); in pkhtb()
8096 Register rn = operand.GetBaseRegister(); in pld() local
8100 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) && in pld()
8110 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) && in pld()
8122 Register rn = operand.GetBaseRegister(); in pld() local
8127 ((rn.GetCode() & 0xf) != 0xf)) { in pld()
8128 EmitT32_32(0xf890f000U | (rn.GetCode() << 16) | (offset & 0xfff)); in pld()
8134 ((rn.GetCode() & 0xf) != 0xf)) { in pld()
8135 EmitT32_32(0xf810fc00U | (rn.GetCode() << 16) | (-offset & 0xff)); in pld()
8142 ((rn.GetCode() & 0xf) != 0xf)) { in pld()
8146 EmitA32(0xf550f000U | (rn.GetCode() << 16) | offset_ | (sign << 23)); in pld()
8153 Register rn = operand.GetBaseRegister(); in pld() local
8161 ((rn.GetCode() & 0xf) != 0xf) && in pld()
8163 EmitT32_32(0xf810f000U | (rn.GetCode() << 16) | rm.GetCode() | in pld()
8175 EmitA32(0xf750f000U | (rn.GetCode() << 16) | rm.GetCode() | in pld()
8185 EmitA32(0xf750f060U | (rn.GetCode() << 16) | rm.GetCode() | in pld()
8199 Register rn = operand.GetBaseRegister(); in pldw() local
8204 ((rn.GetCode() & 0xf) != 0xf)) { in pldw()
8205 EmitT32_32(0xf8b0f000U | (rn.GetCode() << 16) | (offset & 0xfff)); in pldw()
8211 ((rn.GetCode() & 0xf) != 0xf)) { in pldw()
8212 EmitT32_32(0xf830fc00U | (rn.GetCode() << 16) | (-offset & 0xff)); in pldw()
8219 ((rn.GetCode() & 0xf) != 0xf)) { in pldw()
8223 EmitA32(0xf510f000U | (rn.GetCode() << 16) | offset_ | (sign << 23)); in pldw()
8230 Register rn = operand.GetBaseRegister(); in pldw() local
8238 ((rn.GetCode() & 0xf) != 0xf) && in pldw()
8240 EmitT32_32(0xf830f000U | (rn.GetCode() << 16) | rm.GetCode() | in pldw()
8252 EmitA32(0xf710f000U | (rn.GetCode() << 16) | rm.GetCode() | in pldw()
8262 EmitA32(0xf710f060U | (rn.GetCode() << 16) | rm.GetCode() | in pldw()
8276 Register rn = operand.GetBaseRegister(); in pli() local
8281 ((rn.GetCode() & 0xf) != 0xf)) { in pli()
8282 EmitT32_32(0xf990f000U | (rn.GetCode() << 16) | (offset & 0xfff)); in pli()
8288 ((rn.GetCode() & 0xf) != 0xf)) { in pli()
8289 EmitT32_32(0xf910fc00U | (rn.GetCode() << 16) | (-offset & 0xff)); in pli()
8296 ((rn.GetCode() & 0xf) != 0xf)) { in pli()
8300 EmitA32(0xf450f000U | (rn.GetCode() << 16) | offset_ | (sign << 23)); in pli()
8307 Register rn = operand.GetBaseRegister(); in pli() local
8311 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) && in pli()
8321 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) && in pli()
8333 Register rn = operand.GetBaseRegister(); in pli() local
8341 ((rn.GetCode() & 0xf) != 0xf) && in pli()
8343 EmitT32_32(0xf910f000U | (rn.GetCode() << 16) | rm.GetCode() | in pli()
8354 EmitA32(0xf650f060U | (rn.GetCode() << 16) | rm.GetCode() | in pli()
8365 EmitA32(0xf650f000U | (rn.GetCode() << 16) | rm.GetCode() | in pli()
8560 void Assembler::qadd(Condition cond, Register rd, Register rm, Register rn) { in qadd() argument
8565 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qadd()
8567 (rn.GetCode() << 16)); in qadd()
8574 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qadd()
8576 rm.GetCode() | (rn.GetCode() << 16)); in qadd()
8580 Delegate(kQadd, &Assembler::qadd, cond, rd, rm, rn); in qadd()
8583 void Assembler::qadd16(Condition cond, Register rd, Register rn, Register rm) { in qadd16() argument
8588 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qadd16()
8589 EmitT32_32(0xfa90f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in qadd16()
8597 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qadd16()
8599 (rn.GetCode() << 16) | rm.GetCode()); in qadd16()
8603 Delegate(kQadd16, &Assembler::qadd16, cond, rd, rn, rm); in qadd16()
8606 void Assembler::qadd8(Condition cond, Register rd, Register rn, Register rm) { in qadd8() argument
8611 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qadd8()
8612 EmitT32_32(0xfa80f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in qadd8()
8620 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qadd8()
8622 (rn.GetCode() << 16) | rm.GetCode()); in qadd8()
8626 Delegate(kQadd8, &Assembler::qadd8, cond, rd, rn, rm); in qadd8()
8629 void Assembler::qasx(Condition cond, Register rd, Register rn, Register rm) { in qasx() argument
8634 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qasx()
8635 EmitT32_32(0xfaa0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in qasx()
8643 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qasx()
8645 (rn.GetCode() << 16) | rm.GetCode()); in qasx()
8649 Delegate(kQasx, &Assembler::qasx, cond, rd, rn, rm); in qasx()
8652 void Assembler::qdadd(Condition cond, Register rd, Register rm, Register rn) { in qdadd() argument
8657 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qdadd()
8659 (rn.GetCode() << 16)); in qdadd()
8666 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qdadd()
8668 rm.GetCode() | (rn.GetCode() << 16)); in qdadd()
8672 Delegate(kQdadd, &Assembler::qdadd, cond, rd, rm, rn); in qdadd()
8675 void Assembler::qdsub(Condition cond, Register rd, Register rm, Register rn) { in qdsub() argument
8680 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qdsub()
8682 (rn.GetCode() << 16)); in qdsub()
8689 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qdsub()
8691 rm.GetCode() | (rn.GetCode() << 16)); in qdsub()
8695 Delegate(kQdsub, &Assembler::qdsub, cond, rd, rm, rn); in qdsub()
8698 void Assembler::qsax(Condition cond, Register rd, Register rn, Register rm) { in qsax() argument
8703 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsax()
8704 EmitT32_32(0xfae0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in qsax()
8712 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsax()
8714 (rn.GetCode() << 16) | rm.GetCode()); in qsax()
8718 Delegate(kQsax, &Assembler::qsax, cond, rd, rn, rm); in qsax()
8721 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) { in qsub() argument
8726 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsub()
8728 (rn.GetCode() << 16)); in qsub()
8735 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsub()
8737 rm.GetCode() | (rn.GetCode() << 16)); in qsub()
8741 Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn); in qsub()
8744 void Assembler::qsub16(Condition cond, Register rd, Register rn, Register rm) { in qsub16() argument
8749 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsub16()
8750 EmitT32_32(0xfad0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in qsub16()
8758 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsub16()
8760 (rn.GetCode() << 16) | rm.GetCode()); in qsub16()
8764 Delegate(kQsub16, &Assembler::qsub16, cond, rd, rn, rm); in qsub16()
8767 void Assembler::qsub8(Condition cond, Register rd, Register rn, Register rm) { in qsub8() argument
8772 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsub8()
8773 EmitT32_32(0xfac0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in qsub8()
8781 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in qsub8()
8783 (rn.GetCode() << 16) | rm.GetCode()); in qsub8()
8787 Delegate(kQsub8, &Assembler::qsub8, cond, rd, rn, rm); in qsub8()
9073 Register rn, in rsb() argument
9082 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in rsb()
9084 EmitT32_16(0x4240 | rd.GetCode() | (rn.GetCode() << 3)); in rsb()
9090 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in rsb()
9091 EmitT32_32(0xf1c00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in rsb()
9103 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in rsb()
9116 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in rsb()
9118 EmitT32_32(0xebc00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in rsb()
9129 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rsb()
9142 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in rsb()
9145 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rsb()
9151 Delegate(kRsb, &Assembler::rsb, cond, size, rd, rn, operand); in rsb()
9157 Register rn, in rsbs() argument
9166 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in rsbs()
9168 EmitT32_16(0x4240 | rd.GetCode() | (rn.GetCode() << 3)); in rsbs()
9174 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in rsbs()
9175 EmitT32_32(0xf1d00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in rsbs()
9187 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in rsbs()
9200 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in rsbs()
9202 EmitT32_32(0xebd00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in rsbs()
9213 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rsbs()
9226 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in rsbs()
9229 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rsbs()
9235 Delegate(kRsbs, &Assembler::rsbs, cond, size, rd, rn, operand); in rsbs()
9240 Register rn, in rsc() argument
9251 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in rsc()
9266 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rsc()
9279 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in rsc()
9282 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rsc()
9288 Delegate(kRsc, &Assembler::rsc, cond, rd, rn, operand); in rsc()
9293 Register rn, in rscs() argument
9304 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in rscs()
9319 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rscs()
9332 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in rscs()
9335 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in rscs()
9341 Delegate(kRscs, &Assembler::rscs, cond, rd, rn, operand); in rscs()
9344 void Assembler::sadd16(Condition cond, Register rd, Register rn, Register rm) { in sadd16() argument
9349 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sadd16()
9350 EmitT32_32(0xfa90f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sadd16()
9358 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sadd16()
9360 (rn.GetCode() << 16) | rm.GetCode()); in sadd16()
9364 Delegate(kSadd16, &Assembler::sadd16, cond, rd, rn, rm); in sadd16()
9367 void Assembler::sadd8(Condition cond, Register rd, Register rn, Register rm) { in sadd8() argument
9372 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sadd8()
9373 EmitT32_32(0xfa80f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sadd8()
9381 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sadd8()
9383 (rn.GetCode() << 16) | rm.GetCode()); in sadd8()
9387 Delegate(kSadd8, &Assembler::sadd8, cond, rd, rn, rm); in sadd8()
9390 void Assembler::sasx(Condition cond, Register rd, Register rn, Register rm) { in sasx() argument
9395 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sasx()
9396 EmitT32_32(0xfaa0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sasx()
9404 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sasx()
9406 (rn.GetCode() << 16) | rm.GetCode()); in sasx()
9410 Delegate(kSasx, &Assembler::sasx, cond, rd, rn, rm); in sasx()
9416 Register rn, in sbc() argument
9426 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in sbc()
9427 EmitT32_32(0xf1600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sbc()
9439 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in sbc()
9450 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in sbc()
9463 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sbc()
9465 EmitT32_32(0xeb600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sbc()
9476 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sbc()
9489 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in sbc()
9492 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sbc()
9498 Delegate(kSbc, &Assembler::sbc, cond, size, rd, rn, operand); in sbc()
9504 Register rn, in sbcs() argument
9514 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in sbcs()
9515 EmitT32_32(0xf1700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sbcs()
9527 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in sbcs()
9538 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in sbcs()
9551 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sbcs()
9553 EmitT32_32(0xeb700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sbcs()
9564 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sbcs()
9577 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in sbcs()
9580 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sbcs()
9586 Delegate(kSbcs, &Assembler::sbcs, cond, size, rd, rn, operand); in sbcs()
9590 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) { in sbfx() argument
9596 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) || in sbfx()
9599 EmitT32_32(0xf3400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sbfx()
9607 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) || in sbfx()
9611 rn.GetCode() | (lsb << 7) | (widthm1 << 16)); in sbfx()
9615 Delegate(kSbfx, &Assembler::sbfx, cond, rd, rn, lsb, width); in sbfx()
9618 void Assembler::sdiv(Condition cond, Register rd, Register rn, Register rm) { in sdiv() argument
9623 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sdiv()
9624 EmitT32_32(0xfb90f0f0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sdiv()
9632 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sdiv()
9634 rn.GetCode() | (rm.GetCode() << 8)); in sdiv()
9638 Delegate(kSdiv, &Assembler::sdiv, cond, rd, rn, rm); in sdiv()
9641 void Assembler::sel(Condition cond, Register rd, Register rn, Register rm) { in sel() argument
9646 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sel()
9647 EmitT32_32(0xfaa0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sel()
9655 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sel()
9657 (rn.GetCode() << 16) | rm.GetCode()); in sel()
9661 Delegate(kSel, &Assembler::sel, cond, rd, rn, rm); in sel()
9664 void Assembler::shadd16(Condition cond, Register rd, Register rn, Register rm) { in shadd16() argument
9669 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shadd16()
9670 EmitT32_32(0xfa90f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in shadd16()
9678 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shadd16()
9680 (rn.GetCode() << 16) | rm.GetCode()); in shadd16()
9684 Delegate(kShadd16, &Assembler::shadd16, cond, rd, rn, rm); in shadd16()
9687 void Assembler::shadd8(Condition cond, Register rd, Register rn, Register rm) { in shadd8() argument
9692 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shadd8()
9693 EmitT32_32(0xfa80f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in shadd8()
9701 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shadd8()
9703 (rn.GetCode() << 16) | rm.GetCode()); in shadd8()
9707 Delegate(kShadd8, &Assembler::shadd8, cond, rd, rn, rm); in shadd8()
9710 void Assembler::shasx(Condition cond, Register rd, Register rn, Register rm) { in shasx() argument
9715 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shasx()
9716 EmitT32_32(0xfaa0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in shasx()
9724 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shasx()
9726 (rn.GetCode() << 16) | rm.GetCode()); in shasx()
9730 Delegate(kShasx, &Assembler::shasx, cond, rd, rn, rm); in shasx()
9733 void Assembler::shsax(Condition cond, Register rd, Register rn, Register rm) { in shsax() argument
9738 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shsax()
9739 EmitT32_32(0xfae0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in shsax()
9747 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shsax()
9749 (rn.GetCode() << 16) | rm.GetCode()); in shsax()
9753 Delegate(kShsax, &Assembler::shsax, cond, rd, rn, rm); in shsax()
9756 void Assembler::shsub16(Condition cond, Register rd, Register rn, Register rm) { in shsub16() argument
9761 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shsub16()
9762 EmitT32_32(0xfad0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in shsub16()
9770 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shsub16()
9772 (rn.GetCode() << 16) | rm.GetCode()); in shsub16()
9776 Delegate(kShsub16, &Assembler::shsub16, cond, rd, rn, rm); in shsub16()
9779 void Assembler::shsub8(Condition cond, Register rd, Register rn, Register rm) { in shsub8() argument
9784 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shsub8()
9785 EmitT32_32(0xfac0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in shsub8()
9793 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in shsub8()
9795 (rn.GetCode() << 16) | rm.GetCode()); in shsub8()
9799 Delegate(kShsub8, &Assembler::shsub8, cond, rd, rn, rm); in shsub8()
9803 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlabb() argument
9809 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlabb()
9810 EmitT32_32(0xfb100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlabb()
9818 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smlabb()
9821 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlabb()
9825 Delegate(kSmlabb, &Assembler::smlabb, cond, rd, rn, rm, ra); in smlabb()
9829 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlabt() argument
9835 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlabt()
9836 EmitT32_32(0xfb100010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlabt()
9844 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smlabt()
9847 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlabt()
9851 Delegate(kSmlabt, &Assembler::smlabt, cond, rd, rn, rm, ra); in smlabt()
9855 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlad() argument
9861 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlad()
9862 EmitT32_32(0xfb200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlad()
9870 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlad()
9872 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlad()
9876 Delegate(kSmlad, &Assembler::smlad, cond, rd, rn, rm, ra); in smlad()
9880 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smladx() argument
9886 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smladx()
9887 EmitT32_32(0xfb200010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smladx()
9895 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smladx()
9897 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smladx()
9901 Delegate(kSmladx, &Assembler::smladx, cond, rd, rn, rm, ra); in smladx()
9905 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlal() argument
9910 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlal()
9913 (rn.GetCode() << 16) | rm.GetCode()); in smlal()
9920 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlal()
9923 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlal()
9928 Delegate(kSmlal, &Assembler::smlal, cond, rdlo, rdhi, rn, rm); in smlal()
9932 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlalbb() argument
9937 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlalbb()
9940 (rn.GetCode() << 16) | rm.GetCode()); in smlalbb()
9947 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlalbb()
9950 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlalbb()
9955 Delegate(kSmlalbb, &Assembler::smlalbb, cond, rdlo, rdhi, rn, rm); in smlalbb()
9959 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlalbt() argument
9964 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlalbt()
9967 (rn.GetCode() << 16) | rm.GetCode()); in smlalbt()
9974 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlalbt()
9977 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlalbt()
9982 Delegate(kSmlalbt, &Assembler::smlalbt, cond, rdlo, rdhi, rn, rm); in smlalbt()
9986 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlald() argument
9991 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlald()
9994 (rn.GetCode() << 16) | rm.GetCode()); in smlald()
10001 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlald()
10004 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlald()
10009 Delegate(kSmlald, &Assembler::smlald, cond, rdlo, rdhi, rn, rm); in smlald()
10013 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlaldx() argument
10018 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlaldx()
10021 (rn.GetCode() << 16) | rm.GetCode()); in smlaldx()
10028 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlaldx()
10031 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlaldx()
10036 Delegate(kSmlaldx, &Assembler::smlaldx, cond, rdlo, rdhi, rn, rm); in smlaldx()
10040 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlals() argument
10046 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlals()
10049 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlals()
10054 Delegate(kSmlals, &Assembler::smlals, cond, rdlo, rdhi, rn, rm); in smlals()
10058 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlaltb() argument
10063 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlaltb()
10066 (rn.GetCode() << 16) | rm.GetCode()); in smlaltb()
10073 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlaltb()
10076 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlaltb()
10081 Delegate(kSmlaltb, &Assembler::smlaltb, cond, rdlo, rdhi, rn, rm); in smlaltb()
10085 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlaltt() argument
10090 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlaltt()
10093 (rn.GetCode() << 16) | rm.GetCode()); in smlaltt()
10100 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlaltt()
10103 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlaltt()
10108 Delegate(kSmlaltt, &Assembler::smlaltt, cond, rdlo, rdhi, rn, rm); in smlaltt()
10112 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlatb() argument
10118 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlatb()
10119 EmitT32_32(0xfb100020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlatb()
10127 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smlatb()
10130 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlatb()
10134 Delegate(kSmlatb, &Assembler::smlatb, cond, rd, rn, rm, ra); in smlatb()
10138 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlatt() argument
10144 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlatt()
10145 EmitT32_32(0xfb100030U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlatt()
10153 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smlatt()
10156 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlatt()
10160 Delegate(kSmlatt, &Assembler::smlatt, cond, rd, rn, rm, ra); in smlatt()
10164 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlawb() argument
10170 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlawb()
10171 EmitT32_32(0xfb300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlawb()
10179 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smlawb()
10182 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlawb()
10186 Delegate(kSmlawb, &Assembler::smlawb, cond, rd, rn, rm, ra); in smlawb()
10190 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlawt() argument
10196 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlawt()
10197 EmitT32_32(0xfb300010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlawt()
10205 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smlawt()
10208 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlawt()
10212 Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra); in smlawt()
10216 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlsd() argument
10222 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlsd()
10223 EmitT32_32(0xfb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlsd()
10231 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlsd()
10233 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlsd()
10237 Delegate(kSmlsd, &Assembler::smlsd, cond, rd, rn, rm, ra); in smlsd()
10241 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smlsdx() argument
10247 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlsdx()
10248 EmitT32_32(0xfb400010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smlsdx()
10256 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smlsdx()
10258 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smlsdx()
10262 Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra); in smlsdx()
10266 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlsld() argument
10271 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlsld()
10274 (rn.GetCode() << 16) | rm.GetCode()); in smlsld()
10281 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlsld()
10284 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlsld()
10289 Delegate(kSmlsld, &Assembler::smlsld, cond, rdlo, rdhi, rn, rm); in smlsld()
10293 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smlsldx() argument
10298 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlsldx()
10301 (rn.GetCode() << 16) | rm.GetCode()); in smlsldx()
10308 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smlsldx()
10311 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smlsldx()
10316 Delegate(kSmlsldx, &Assembler::smlsldx, cond, rdlo, rdhi, rn, rm); in smlsldx()
10320 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smmla() argument
10326 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmla()
10327 EmitT32_32(0xfb500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smmla()
10335 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmla()
10337 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smmla()
10341 Delegate(kSmmla, &Assembler::smmla, cond, rd, rn, rm, ra); in smmla()
10345 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smmlar() argument
10351 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmlar()
10352 EmitT32_32(0xfb500010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smmlar()
10360 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmlar()
10362 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smmlar()
10366 Delegate(kSmmlar, &Assembler::smmlar, cond, rd, rn, rm, ra); in smmlar()
10370 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smmls() argument
10375 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smmls()
10377 EmitT32_32(0xfb600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smmls()
10385 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smmls()
10388 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smmls()
10392 Delegate(kSmmls, &Assembler::smmls, cond, rd, rn, rm, ra); in smmls()
10396 Condition cond, Register rd, Register rn, Register rm, Register ra) { in smmlsr() argument
10401 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smmlsr()
10403 EmitT32_32(0xfb600010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smmlsr()
10411 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) || in smmlsr()
10414 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in smmlsr()
10418 Delegate(kSmmlsr, &Assembler::smmlsr, cond, rd, rn, rm, ra); in smmlsr()
10421 void Assembler::smmul(Condition cond, Register rd, Register rn, Register rm) { in smmul() argument
10426 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmul()
10427 EmitT32_32(0xfb50f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smmul()
10435 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmul()
10437 rn.GetCode() | (rm.GetCode() << 8)); in smmul()
10441 Delegate(kSmmul, &Assembler::smmul, cond, rd, rn, rm); in smmul()
10444 void Assembler::smmulr(Condition cond, Register rd, Register rn, Register rm) { in smmulr() argument
10449 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmulr()
10450 EmitT32_32(0xfb50f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smmulr()
10458 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smmulr()
10460 rn.GetCode() | (rm.GetCode() << 8)); in smmulr()
10464 Delegate(kSmmulr, &Assembler::smmulr, cond, rd, rn, rm); in smmulr()
10467 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) { in smuad() argument
10472 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smuad()
10473 EmitT32_32(0xfb20f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smuad()
10481 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smuad()
10483 rn.GetCode() | (rm.GetCode() << 8)); in smuad()
10487 Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm); in smuad()
10490 void Assembler::smuadx(Condition cond, Register rd, Register rn, Register rm) { in smuadx() argument
10495 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smuadx()
10496 EmitT32_32(0xfb20f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smuadx()
10504 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smuadx()
10506 rn.GetCode() | (rm.GetCode() << 8)); in smuadx()
10510 Delegate(kSmuadx, &Assembler::smuadx, cond, rd, rn, rm); in smuadx()
10513 void Assembler::smulbb(Condition cond, Register rd, Register rn, Register rm) { in smulbb() argument
10518 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulbb()
10519 EmitT32_32(0xfb10f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smulbb()
10527 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulbb()
10529 rn.GetCode() | (rm.GetCode() << 8)); in smulbb()
10533 Delegate(kSmulbb, &Assembler::smulbb, cond, rd, rn, rm); in smulbb()
10536 void Assembler::smulbt(Condition cond, Register rd, Register rn, Register rm) { in smulbt() argument
10541 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulbt()
10542 EmitT32_32(0xfb10f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smulbt()
10550 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulbt()
10552 rn.GetCode() | (rm.GetCode() << 8)); in smulbt()
10556 Delegate(kSmulbt, &Assembler::smulbt, cond, rd, rn, rm); in smulbt()
10560 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smull() argument
10565 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smull()
10568 (rn.GetCode() << 16) | rm.GetCode()); in smull()
10575 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smull()
10578 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smull()
10583 Delegate(kSmull, &Assembler::smull, cond, rdlo, rdhi, rn, rm); in smull()
10587 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in smulls() argument
10593 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in smulls()
10596 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in smulls()
10601 Delegate(kSmulls, &Assembler::smulls, cond, rdlo, rdhi, rn, rm); in smulls()
10604 void Assembler::smultb(Condition cond, Register rd, Register rn, Register rm) { in smultb() argument
10609 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smultb()
10610 EmitT32_32(0xfb10f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smultb()
10618 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smultb()
10620 rn.GetCode() | (rm.GetCode() << 8)); in smultb()
10624 Delegate(kSmultb, &Assembler::smultb, cond, rd, rn, rm); in smultb()
10627 void Assembler::smultt(Condition cond, Register rd, Register rn, Register rm) { in smultt() argument
10632 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smultt()
10633 EmitT32_32(0xfb10f030U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smultt()
10641 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smultt()
10643 rn.GetCode() | (rm.GetCode() << 8)); in smultt()
10647 Delegate(kSmultt, &Assembler::smultt, cond, rd, rn, rm); in smultt()
10650 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) { in smulwb() argument
10655 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulwb()
10656 EmitT32_32(0xfb30f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smulwb()
10664 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulwb()
10666 rn.GetCode() | (rm.GetCode() << 8)); in smulwb()
10670 Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm); in smulwb()
10673 void Assembler::smulwt(Condition cond, Register rd, Register rn, Register rm) { in smulwt() argument
10678 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulwt()
10679 EmitT32_32(0xfb30f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smulwt()
10687 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smulwt()
10689 rn.GetCode() | (rm.GetCode() << 8)); in smulwt()
10693 Delegate(kSmulwt, &Assembler::smulwt, cond, rd, rn, rm); in smulwt()
10696 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) { in smusd() argument
10701 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smusd()
10702 EmitT32_32(0xfb40f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smusd()
10710 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smusd()
10712 rn.GetCode() | (rm.GetCode() << 8)); in smusd()
10716 Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm); in smusd()
10719 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) { in smusdx() argument
10724 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smusdx()
10725 EmitT32_32(0xfb40f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in smusdx()
10733 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in smusdx()
10735 rn.GetCode() | (rm.GetCode() << 8)); in smusdx()
10739 Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm); in smusdx()
10749 Register rn = operand.GetBaseRegister(); in ssat() local
10756 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ssat()
10759 (rn.GetCode() << 16) | ((amount & 0x3) << 6) | in ssat()
10766 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ssat()
10769 (rn.GetCode() << 16) | ((amount & 0x3) << 6) | in ssat()
10778 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ssat()
10782 (rd.GetCode() << 12) | (imm_ << 16) | rn.GetCode() | in ssat()
10789 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ssat()
10792 (rd.GetCode() << 12) | (imm_ << 16) | rn.GetCode() | in ssat()
10801 void Assembler::ssat16(Condition cond, Register rd, uint32_t imm, Register rn) { in ssat16() argument
10807 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ssat16()
10810 (rn.GetCode() << 16)); in ssat16()
10817 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in ssat16()
10820 (imm_ << 16) | rn.GetCode()); in ssat16()
10824 Delegate(kSsat16, &Assembler::ssat16, cond, rd, imm, rn); in ssat16()
10827 void Assembler::ssax(Condition cond, Register rd, Register rn, Register rm) { in ssax() argument
10832 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in ssax()
10833 EmitT32_32(0xfae0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in ssax()
10841 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in ssax()
10843 (rn.GetCode() << 16) | rm.GetCode()); in ssax()
10847 Delegate(kSsax, &Assembler::ssax, cond, rd, rn, rm); in ssax()
10850 void Assembler::ssub16(Condition cond, Register rd, Register rn, Register rm) { in ssub16() argument
10855 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in ssub16()
10856 EmitT32_32(0xfad0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in ssub16()
10864 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in ssub16()
10866 (rn.GetCode() << 16) | rm.GetCode()); in ssub16()
10870 Delegate(kSsub16, &Assembler::ssub16, cond, rd, rn, rm); in ssub16()
10873 void Assembler::ssub8(Condition cond, Register rd, Register rn, Register rm) { in ssub8() argument
10878 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in ssub8()
10879 EmitT32_32(0xfac0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in ssub8()
10887 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in ssub8()
10889 (rn.GetCode() << 16) | rm.GetCode()); in ssub8()
10893 Delegate(kSsub8, &Assembler::ssub8, cond, rd, rn, rm); in ssub8()
10900 Register rn = operand.GetBaseRegister(); in stl() local
10904 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stl()
10905 EmitT32_32(0xe8c00fafU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in stl()
10912 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stl()
10914 (rn.GetCode() << 16)); in stl()
10926 Register rn = operand.GetBaseRegister(); in stlb() local
10930 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlb()
10931 EmitT32_32(0xe8c00f8fU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in stlb()
10938 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlb()
10940 (rn.GetCode() << 16)); in stlb()
10955 Register rn = operand.GetBaseRegister(); in stlex() local
10959 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlex()
10961 (rn.GetCode() << 16)); in stlex()
10968 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlex()
10970 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in stlex()
10985 Register rn = operand.GetBaseRegister(); in stlexb() local
10989 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlexb()
10991 (rn.GetCode() << 16)); in stlexb()
10998 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlexb()
11000 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in stlexb()
11016 Register rn = operand.GetBaseRegister(); in stlexd() local
11020 ((!rd.IsPC() && !rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) || in stlexd()
11023 (rt2.GetCode() << 8) | (rn.GetCode() << 16)); in stlexd()
11032 !rn.IsPC()) || in stlexd()
11035 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in stlexd()
11050 Register rn = operand.GetBaseRegister(); in stlexh() local
11054 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlexh()
11056 (rn.GetCode() << 16)); in stlexh()
11063 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlexh()
11065 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in stlexh()
11077 Register rn = operand.GetBaseRegister(); in stlh() local
11081 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlh()
11082 EmitT32_32(0xe8c00f9fU | (rt.GetCode() << 12) | (rn.GetCode() << 16)); in stlh()
11089 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in stlh()
11091 (rn.GetCode() << 16)); in stlh()
11101 Register rn, in stm() argument
11108 if (!size.IsWide() && rn.IsLow() && write_back.DoesWriteBack() && in stm()
11110 EmitT32_16(0xc000 | (rn.GetCode() << 8) | in stm()
11117 (!rn.IsPC() || AllowUnpredictable())) { in stm()
11118 EmitT32_32(0xe8800000U | (rn.GetCode() << 16) | in stm()
11127 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stm()
11128 EmitA32(0x08800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stm()
11134 Delegate(kStm, &Assembler::stm, cond, size, rn, write_back, registers); in stm()
11138 Register rn, in stmda() argument
11145 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stmda()
11146 EmitA32(0x08000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stmda()
11152 Delegate(kStmda, &Assembler::stmda, cond, rn, write_back, registers); in stmda()
11157 Register rn, in stmdb() argument
11164 if (!size.IsWide() && rn.Is(sp) && write_back.DoesWriteBack() && in stmdb()
11173 (!rn.IsPC() || AllowUnpredictable())) { in stmdb()
11174 EmitT32_32(0xe9000000U | (rn.GetCode() << 16) | in stmdb()
11183 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stmdb()
11184 EmitA32(0x09000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stmdb()
11190 Delegate(kStmdb, &Assembler::stmdb, cond, size, rn, write_back, registers); in stmdb()
11195 Register rn, in stmea() argument
11202 if (!size.IsWide() && rn.IsLow() && write_back.DoesWriteBack() && in stmea()
11204 EmitT32_16(0xc000 | (rn.GetCode() << 8) | in stmea()
11211 (!rn.IsPC() || AllowUnpredictable())) { in stmea()
11212 EmitT32_32(0xe8800000U | (rn.GetCode() << 16) | in stmea()
11221 (!rn.IsPC() || AllowUnpredictable())) { in stmea()
11222 EmitT32_32(0xe8800000U | (rn.GetCode() << 16) | in stmea()
11231 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stmea()
11232 EmitA32(0x08800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stmea()
11238 Delegate(kStmea, &Assembler::stmea, cond, size, rn, write_back, registers); in stmea()
11242 Register rn, in stmed() argument
11249 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stmed()
11250 EmitA32(0x08000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stmed()
11256 Delegate(kStmed, &Assembler::stmed, cond, rn, write_back, registers); in stmed()
11260 Register rn, in stmfa() argument
11267 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stmfa()
11268 EmitA32(0x09800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stmfa()
11274 Delegate(kStmfa, &Assembler::stmfa, cond, rn, write_back, registers); in stmfa()
11278 Register rn, in stmfd() argument
11286 (!rn.IsPC() || AllowUnpredictable())) { in stmfd()
11287 EmitT32_32(0xe9000000U | (rn.GetCode() << 16) | in stmfd()
11296 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stmfd()
11297 EmitA32(0x09000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stmfd()
11303 Delegate(kStmfd, &Assembler::stmfd, cond, rn, write_back, registers); in stmfd()
11307 Register rn, in stmib() argument
11314 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) { in stmib()
11315 EmitA32(0x09800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in stmib()
11321 Delegate(kStmib, &Assembler::stmib, cond, rn, write_back, registers); in stmib()
11331 Register rn = operand.GetBaseRegister(); in str() local
11335 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) && in str()
11338 EmitT32_16(0x6000 | rt.GetCode() | (rn.GetCode() << 3) | in str()
11345 ((offset % 4) == 0) && rn.Is(sp) && operand.IsOffset()) { in str()
11353 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in str()
11355 EmitT32_32(0xf8c00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in str()
11362 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in str()
11364 EmitT32_32(0xf8400c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in str()
11371 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) && in str()
11375 EmitT32_32(0xf8400900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in str()
11382 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) && in str()
11386 EmitT32_32(0xf8400d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in str()
11398 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in str()
11408 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in str()
11418 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in str()
11425 Register rn = operand.GetBaseRegister(); in str() local
11430 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in str()
11432 EmitT32_16(0x5000 | rt.GetCode() | (rn.GetCode() << 3) | in str()
11440 Register rn = operand.GetBaseRegister(); in str() local
11448 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in str()
11450 EmitT32_32(0xf8400000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in str()
11463 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in str()
11474 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in str()
11485 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in str()
11501 Register rn = operand.GetBaseRegister(); in strb() local
11505 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) && in strb()
11507 EmitT32_16(0x7000 | rt.GetCode() | (rn.GetCode() << 3) | in strb()
11514 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in strb()
11516 EmitT32_32(0xf8800000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strb()
11523 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in strb()
11525 EmitT32_32(0xf8000c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strb()
11532 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) && in strb()
11536 EmitT32_32(0xf8000900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strb()
11543 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) && in strb()
11547 EmitT32_32(0xf8000d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strb()
11559 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in strb()
11569 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in strb()
11579 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ | in strb()
11586 Register rn = operand.GetBaseRegister(); in strb() local
11591 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in strb()
11593 EmitT32_16(0x5400 | rt.GetCode() | (rn.GetCode() << 3) | in strb()
11601 Register rn = operand.GetBaseRegister(); in strb() local
11609 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in strb()
11611 EmitT32_32(0xf8000000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strb()
11624 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strb()
11636 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strb()
11647 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strb()
11663 Register rn = operand.GetBaseRegister(); in strd() local
11668 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in strd()
11669 ((!rn.IsPC() && !rt.IsPC() && !rt2.IsPC()) || AllowUnpredictable())) { in strd()
11673 (rn.GetCode() << 16) | offset_ | (sign << 23)); in strd()
11679 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) && in strd()
11680 ((!rn.IsPC() && !rt.IsPC() && !rt2.IsPC()) || AllowUnpredictable())) { in strd()
11684 (rn.GetCode() << 16) | offset_ | (sign << 23)); in strd()
11690 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) && in strd()
11691 ((!rn.IsPC() && !rt.IsPC() && !rt2.IsPC()) || AllowUnpredictable())) { in strd()
11695 (rn.GetCode() << 16) | offset_ | (sign << 23)); in strd()
11708 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in strd()
11720 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in strd()
11732 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in strd()
11739 Register rn = operand.GetBaseRegister(); in strd() local
11750 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strd()
11761 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strd()
11772 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strd()
11788 Register rn = operand.GetBaseRegister(); in strex() local
11794 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in strex()
11797 (rn.GetCode() << 16) | (offset_ & 0xff)); in strex()
11804 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in strex()
11806 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in strex()
11821 Register rn = operand.GetBaseRegister(); in strexb() local
11825 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in strexb()
11827 (rn.GetCode() << 16)); in strexb()
11834 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in strexb()
11836 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in strexb()
11852 Register rn = operand.GetBaseRegister(); in strexd() local
11856 ((!rd.IsPC() && !rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) || in strexd()
11859 (rt2.GetCode() << 8) | (rn.GetCode() << 16)); in strexd()
11868 !rn.IsPC()) || in strexd()
11871 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in strexd()
11886 Register rn = operand.GetBaseRegister(); in strexh() local
11890 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in strexh()
11892 (rn.GetCode() << 16)); in strexh()
11899 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in strexh()
11901 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16)); in strexh()
11916 Register rn = operand.GetBaseRegister(); in strh() local
11920 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) && in strh()
11923 EmitT32_16(0x8000 | rt.GetCode() | (rn.GetCode() << 3) | in strh()
11930 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in strh()
11932 EmitT32_32(0xf8a00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strh()
11939 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in strh()
11941 EmitT32_32(0xf8200c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strh()
11948 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) && in strh()
11952 EmitT32_32(0xf8200900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strh()
11959 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) && in strh()
11963 EmitT32_32(0xf8200d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strh()
11975 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in strh()
11985 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in strh()
11995 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) | in strh()
12002 Register rn = operand.GetBaseRegister(); in strh() local
12007 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() && in strh()
12009 EmitT32_16(0x5200 | rt.GetCode() | (rn.GetCode() << 3) | in strh()
12020 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strh()
12029 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strh()
12038 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in strh()
12045 Register rn = operand.GetBaseRegister(); in strh() local
12053 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && in strh()
12055 EmitT32_32(0xf8200000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) | in strh()
12068 Register rn, in sub() argument
12077 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in sub()
12079 EmitT32_16(0x1e00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6)); in sub()
12084 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in sub()
12091 if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && (imm <= 508) && in sub()
12099 if (!size.IsNarrow() && rn.Is(pc) && (imm <= 4095) && in sub()
12107 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) && in sub()
12108 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in sub()
12109 EmitT32_32(0xf1a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sub()
12117 if (!size.IsNarrow() && (imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) && in sub()
12119 EmitT32_32(0xf2a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sub()
12125 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() && in sub()
12135 if (!size.IsNarrow() && rn.Is(sp) && (imm <= 4095) && in sub()
12145 if (rn.Is(pc) && immediate_a32.IsValid() && cond.IsNotNever()) { in sub()
12152 ((rn.GetCode() & 0xd) != 0xd)) { in sub()
12154 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in sub()
12159 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) { in sub()
12171 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in sub()
12173 EmitT32_16(0x1a00 | rd.GetCode() | (rn.GetCode() << 3) | in sub()
12179 if (rn.Is(sp) && ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sub()
12190 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) && in sub()
12191 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in sub()
12193 EmitT32_32(0xeba00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sub()
12200 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) && in sub()
12211 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) { in sub()
12214 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sub()
12219 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) { in sub()
12235 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in sub()
12238 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sub()
12244 Delegate(kSub, &Assembler::sub, cond, size, rd, rn, operand); in sub()
12267 Register rn, in subs() argument
12276 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in subs()
12278 EmitT32_16(0x1e00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6)); in subs()
12283 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in subs()
12290 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) && in subs()
12291 !rd.Is(pc) && (!rn.IsPC() || AllowUnpredictable())) { in subs()
12292 EmitT32_32(0xf1b00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in subs()
12300 if (!size.IsNarrow() && rd.Is(pc) && rn.Is(lr) && (imm <= 255) && in subs()
12307 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() && in subs()
12319 if (immediate_a32.IsValid() && cond.IsNotNever() && !rn.Is(sp)) { in subs()
12321 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in subs()
12326 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) { in subs()
12338 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() && in subs()
12340 EmitT32_16(0x1a00 | rd.GetCode() | (rn.GetCode() << 3) | in subs()
12351 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) && in subs()
12352 !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in subs()
12354 EmitT32_32(0xebb00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in subs()
12361 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) && in subs()
12372 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) { in subs()
12375 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in subs()
12380 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) { in subs()
12396 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in subs()
12399 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in subs()
12405 Delegate(kSubs, &Assembler::subs, cond, size, rd, rn, operand); in subs()
12427 Register rn, in subw() argument
12435 if ((imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) && in subw()
12437 EmitT32_32(0xf2a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in subw()
12443 if (rn.Is(sp) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) { in subw()
12451 Delegate(kSubw, &Assembler::subw, cond, rd, rn, operand); in subw()
12476 Register rn, in sxtab() argument
12487 ((amount % 8) == 0) && !rn.Is(pc) && in sxtab()
12490 EmitT32_32(0xfa40f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sxtab()
12498 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) && in sxtab()
12502 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sxtab()
12508 Delegate(kSxtab, &Assembler::sxtab, cond, rd, rn, operand); in sxtab()
12513 Register rn, in sxtab16() argument
12524 ((amount % 8) == 0) && !rn.Is(pc) && in sxtab16()
12527 EmitT32_32(0xfa20f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sxtab16()
12535 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) && in sxtab16()
12539 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sxtab16()
12545 Delegate(kSxtab16, &Assembler::sxtab16, cond, rd, rn, operand); in sxtab16()
12550 Register rn, in sxtah() argument
12561 ((amount % 8) == 0) && !rn.Is(pc) && in sxtah()
12564 EmitT32_32(0xfa00f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in sxtah()
12572 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) && in sxtah()
12576 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in sxtah()
12582 Delegate(kSxtah, &Assembler::sxtah, cond, rd, rn, operand); in sxtah()
12710 void Assembler::tbb(Condition cond, Register rn, Register rm) { in tbb() argument
12717 EmitT32_32(0xe8d0f000U | (rn.GetCode() << 16) | rm.GetCode()); in tbb()
12722 Delegate(kTbb, &Assembler::tbb, cond, rn, rm); in tbb()
12725 void Assembler::tbh(Condition cond, Register rn, Register rm) { in tbh() argument
12732 EmitT32_32(0xe8d0f010U | (rn.GetCode() << 16) | rm.GetCode()); in tbh()
12737 Delegate(kTbh, &Assembler::tbh, cond, rn, rm); in tbh()
12740 void Assembler::teq(Condition cond, Register rn, const Operand& operand) { in teq() argument
12748 if (immediate_t32.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in teq()
12749 EmitT32_32(0xf0900f00U | (rn.GetCode() << 16) | in teq()
12761 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue()); in teq()
12773 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in teq()
12775 EmitT32_32(0xea900f00U | (rn.GetCode() << 16) | rm.GetCode() | in teq()
12786 (rn.GetCode() << 16) | rm.GetCode() | in teq()
12799 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) { in teq()
12801 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) | in teq()
12807 Delegate(kTeq, &Assembler::teq, cond, rn, operand); in teq()
12812 Register rn, in tst() argument
12822 (!rn.IsPC() || AllowUnpredictable())) { in tst()
12823 EmitT32_32(0xf0100f00U | (rn.GetCode() << 16) | in tst()
12835 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue()); in tst()
12845 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) { in tst()
12846 EmitT32_16(0x4200 | rn.GetCode() | (rm.GetCode() << 3)); in tst()
12857 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in tst()
12859 EmitT32_32(0xea100f00U | (rn.GetCode() << 16) | rm.GetCode() | in tst()
12870 (rn.GetCode() << 16) | rm.GetCode() | in tst()
12883 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) { in tst()
12885 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) | in tst()
12891 Delegate(kTst, &Assembler::tst, cond, size, rn, operand); in tst()
12894 void Assembler::uadd16(Condition cond, Register rd, Register rn, Register rm) { in uadd16() argument
12899 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uadd16()
12900 EmitT32_32(0xfa90f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uadd16()
12908 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uadd16()
12910 (rn.GetCode() << 16) | rm.GetCode()); in uadd16()
12914 Delegate(kUadd16, &Assembler::uadd16, cond, rd, rn, rm); in uadd16()
12917 void Assembler::uadd8(Condition cond, Register rd, Register rn, Register rm) { in uadd8() argument
12922 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uadd8()
12923 EmitT32_32(0xfa80f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uadd8()
12931 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uadd8()
12933 (rn.GetCode() << 16) | rm.GetCode()); in uadd8()
12937 Delegate(kUadd8, &Assembler::uadd8, cond, rd, rn, rm); in uadd8()
12940 void Assembler::uasx(Condition cond, Register rd, Register rn, Register rm) { in uasx() argument
12945 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uasx()
12946 EmitT32_32(0xfaa0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uasx()
12954 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uasx()
12956 (rn.GetCode() << 16) | rm.GetCode()); in uasx()
12960 Delegate(kUasx, &Assembler::uasx, cond, rd, rn, rm); in uasx()
12964 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) { in ubfx() argument
12970 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) || in ubfx()
12973 EmitT32_32(0xf3c00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in ubfx()
12981 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) || in ubfx()
12985 rn.GetCode() | (lsb << 7) | (widthm1 << 16)); in ubfx()
12989 Delegate(kUbfx, &Assembler::ubfx, cond, rd, rn, lsb, width); in ubfx()
13024 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) { in udiv() argument
13029 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in udiv()
13030 EmitT32_32(0xfbb0f0f0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in udiv()
13038 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in udiv()
13040 rn.GetCode() | (rm.GetCode() << 8)); in udiv()
13044 Delegate(kUdiv, &Assembler::udiv, cond, rd, rn, rm); in udiv()
13047 void Assembler::uhadd16(Condition cond, Register rd, Register rn, Register rm) { in uhadd16() argument
13052 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhadd16()
13053 EmitT32_32(0xfa90f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uhadd16()
13061 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhadd16()
13063 (rn.GetCode() << 16) | rm.GetCode()); in uhadd16()
13067 Delegate(kUhadd16, &Assembler::uhadd16, cond, rd, rn, rm); in uhadd16()
13070 void Assembler::uhadd8(Condition cond, Register rd, Register rn, Register rm) { in uhadd8() argument
13075 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhadd8()
13076 EmitT32_32(0xfa80f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uhadd8()
13084 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhadd8()
13086 (rn.GetCode() << 16) | rm.GetCode()); in uhadd8()
13090 Delegate(kUhadd8, &Assembler::uhadd8, cond, rd, rn, rm); in uhadd8()
13093 void Assembler::uhasx(Condition cond, Register rd, Register rn, Register rm) { in uhasx() argument
13098 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhasx()
13099 EmitT32_32(0xfaa0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uhasx()
13107 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhasx()
13109 (rn.GetCode() << 16) | rm.GetCode()); in uhasx()
13113 Delegate(kUhasx, &Assembler::uhasx, cond, rd, rn, rm); in uhasx()
13116 void Assembler::uhsax(Condition cond, Register rd, Register rn, Register rm) { in uhsax() argument
13121 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhsax()
13122 EmitT32_32(0xfae0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uhsax()
13130 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhsax()
13132 (rn.GetCode() << 16) | rm.GetCode()); in uhsax()
13136 Delegate(kUhsax, &Assembler::uhsax, cond, rd, rn, rm); in uhsax()
13139 void Assembler::uhsub16(Condition cond, Register rd, Register rn, Register rm) { in uhsub16() argument
13144 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhsub16()
13145 EmitT32_32(0xfad0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uhsub16()
13153 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhsub16()
13155 (rn.GetCode() << 16) | rm.GetCode()); in uhsub16()
13159 Delegate(kUhsub16, &Assembler::uhsub16, cond, rd, rn, rm); in uhsub16()
13162 void Assembler::uhsub8(Condition cond, Register rd, Register rn, Register rm) { in uhsub8() argument
13167 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhsub8()
13168 EmitT32_32(0xfac0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uhsub8()
13176 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uhsub8()
13178 (rn.GetCode() << 16) | rm.GetCode()); in uhsub8()
13182 Delegate(kUhsub8, &Assembler::uhsub8, cond, rd, rn, rm); in uhsub8()
13186 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in umaal() argument
13191 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umaal()
13194 (rn.GetCode() << 16) | rm.GetCode()); in umaal()
13201 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umaal()
13204 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in umaal()
13209 Delegate(kUmaal, &Assembler::umaal, cond, rdlo, rdhi, rn, rm); in umaal()
13213 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in umlal() argument
13218 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umlal()
13221 (rn.GetCode() << 16) | rm.GetCode()); in umlal()
13228 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umlal()
13231 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in umlal()
13236 Delegate(kUmlal, &Assembler::umlal, cond, rdlo, rdhi, rn, rm); in umlal()
13240 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in umlals() argument
13246 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umlals()
13249 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in umlals()
13254 Delegate(kUmlals, &Assembler::umlals, cond, rdlo, rdhi, rn, rm); in umlals()
13258 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in umull() argument
13263 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umull()
13266 (rn.GetCode() << 16) | rm.GetCode()); in umull()
13273 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umull()
13276 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in umull()
13281 Delegate(kUmull, &Assembler::umull, cond, rdlo, rdhi, rn, rm); in umull()
13285 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { in umulls() argument
13291 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) || in umulls()
13294 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() | in umulls()
13299 Delegate(kUmulls, &Assembler::umulls, cond, rdlo, rdhi, rn, rm); in umulls()
13302 void Assembler::uqadd16(Condition cond, Register rd, Register rn, Register rm) { in uqadd16() argument
13307 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqadd16()
13308 EmitT32_32(0xfa90f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uqadd16()
13316 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqadd16()
13318 (rn.GetCode() << 16) | rm.GetCode()); in uqadd16()
13322 Delegate(kUqadd16, &Assembler::uqadd16, cond, rd, rn, rm); in uqadd16()
13325 void Assembler::uqadd8(Condition cond, Register rd, Register rn, Register rm) { in uqadd8() argument
13330 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqadd8()
13331 EmitT32_32(0xfa80f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uqadd8()
13339 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqadd8()
13341 (rn.GetCode() << 16) | rm.GetCode()); in uqadd8()
13345 Delegate(kUqadd8, &Assembler::uqadd8, cond, rd, rn, rm); in uqadd8()
13348 void Assembler::uqasx(Condition cond, Register rd, Register rn, Register rm) { in uqasx() argument
13353 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqasx()
13354 EmitT32_32(0xfaa0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uqasx()
13362 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqasx()
13364 (rn.GetCode() << 16) | rm.GetCode()); in uqasx()
13368 Delegate(kUqasx, &Assembler::uqasx, cond, rd, rn, rm); in uqasx()
13371 void Assembler::uqsax(Condition cond, Register rd, Register rn, Register rm) { in uqsax() argument
13376 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqsax()
13377 EmitT32_32(0xfae0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uqsax()
13385 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqsax()
13387 (rn.GetCode() << 16) | rm.GetCode()); in uqsax()
13391 Delegate(kUqsax, &Assembler::uqsax, cond, rd, rn, rm); in uqsax()
13394 void Assembler::uqsub16(Condition cond, Register rd, Register rn, Register rm) { in uqsub16() argument
13399 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqsub16()
13400 EmitT32_32(0xfad0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uqsub16()
13408 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqsub16()
13410 (rn.GetCode() << 16) | rm.GetCode()); in uqsub16()
13414 Delegate(kUqsub16, &Assembler::uqsub16, cond, rd, rn, rm); in uqsub16()
13417 void Assembler::uqsub8(Condition cond, Register rd, Register rn, Register rm) { in uqsub8() argument
13422 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqsub8()
13423 EmitT32_32(0xfac0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uqsub8()
13431 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in uqsub8()
13433 (rn.GetCode() << 16) | rm.GetCode()); in uqsub8()
13437 Delegate(kUqsub8, &Assembler::uqsub8, cond, rd, rn, rm); in uqsub8()
13440 void Assembler::usad8(Condition cond, Register rd, Register rn, Register rm) { in usad8() argument
13445 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usad8()
13446 EmitT32_32(0xfb70f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in usad8()
13454 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usad8()
13456 rn.GetCode() | (rm.GetCode() << 8)); in usad8()
13460 Delegate(kUsad8, &Assembler::usad8, cond, rd, rn, rm); in usad8()
13464 Condition cond, Register rd, Register rn, Register rm, Register ra) { in usada8() argument
13470 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usada8()
13471 EmitT32_32(0xfb700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in usada8()
13479 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usada8()
13481 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12)); in usada8()
13485 Delegate(kUsada8, &Assembler::usada8, cond, rd, rn, rm, ra); in usada8()
13495 Register rn = operand.GetBaseRegister(); in usat() local
13501 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in usat()
13503 (rn.GetCode() << 16) | ((amount & 0x3) << 6) | in usat()
13510 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in usat()
13512 (rn.GetCode() << 16) | ((amount & 0x3) << 6) | in usat()
13521 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in usat()
13524 (rd.GetCode() << 12) | (imm << 16) | rn.GetCode() | in usat()
13530 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in usat()
13532 (rd.GetCode() << 12) | (imm << 16) | rn.GetCode() | in usat()
13541 void Assembler::usat16(Condition cond, Register rd, uint32_t imm, Register rn) { in usat16() argument
13546 if ((imm <= 15) && ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in usat16()
13548 (rn.GetCode() << 16)); in usat16()
13555 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in usat16()
13557 (imm << 16) | rn.GetCode()); in usat16()
13561 Delegate(kUsat16, &Assembler::usat16, cond, rd, imm, rn); in usat16()
13564 void Assembler::usax(Condition cond, Register rd, Register rn, Register rm) { in usax() argument
13569 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usax()
13570 EmitT32_32(0xfae0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in usax()
13578 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usax()
13580 (rn.GetCode() << 16) | rm.GetCode()); in usax()
13584 Delegate(kUsax, &Assembler::usax, cond, rd, rn, rm); in usax()
13587 void Assembler::usub16(Condition cond, Register rd, Register rn, Register rm) { in usub16() argument
13592 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usub16()
13593 EmitT32_32(0xfad0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in usub16()
13601 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usub16()
13603 (rn.GetCode() << 16) | rm.GetCode()); in usub16()
13607 Delegate(kUsub16, &Assembler::usub16, cond, rd, rn, rm); in usub16()
13610 void Assembler::usub8(Condition cond, Register rd, Register rn, Register rm) { in usub8() argument
13615 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usub8()
13616 EmitT32_32(0xfac0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in usub8()
13624 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in usub8()
13626 (rn.GetCode() << 16) | rm.GetCode()); in usub8()
13630 Delegate(kUsub8, &Assembler::usub8, cond, rd, rn, rm); in usub8()
13635 Register rn, in uxtab() argument
13646 ((amount % 8) == 0) && !rn.Is(pc) && in uxtab()
13649 EmitT32_32(0xfa50f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uxtab()
13657 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) && in uxtab()
13661 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in uxtab()
13667 Delegate(kUxtab, &Assembler::uxtab, cond, rd, rn, operand); in uxtab()
13672 Register rn, in uxtab16() argument
13683 ((amount % 8) == 0) && !rn.Is(pc) && in uxtab16()
13686 EmitT32_32(0xfa30f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uxtab16()
13694 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) && in uxtab16()
13698 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in uxtab16()
13704 Delegate(kUxtab16, &Assembler::uxtab16, cond, rd, rn, operand); in uxtab16()
13709 Register rn, in uxtah() argument
13720 ((amount % 8) == 0) && !rn.Is(pc) && in uxtah()
13723 EmitT32_32(0xfa10f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in uxtah()
13731 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) && in uxtah()
13735 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in uxtah()
13741 Delegate(kUxtah, &Assembler::uxtah, cond, rd, rn, operand); in uxtah()
13870 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vaba() argument
13880 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaba()
13891 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaba()
13896 Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm); in vaba()
13900 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vaba() argument
13910 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaba()
13921 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaba()
13926 Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm); in vaba()
13930 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vabal() argument
13940 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabal()
13951 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabal()
13956 Delegate(kVabal, &Assembler::vabal, cond, dt, rd, rn, rm); in vabal()
13960 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vabd() argument
13968 EmitT32_32(0xff200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vabd()
13979 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabd()
13988 EmitA32(0xf3200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vabd()
13998 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabd()
14003 Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm); in vabd()
14007 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vabd() argument
14015 EmitT32_32(0xff200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vabd()
14026 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabd()
14035 EmitA32(0xf3200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vabd()
14045 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabd()
14050 Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm); in vabd()
14054 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vabdl() argument
14064 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabdl()
14075 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vabdl()
14080 Delegate(kVabdl, &Assembler::vabdl, cond, dt, rd, rn, rm); in vabdl()
14175 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vacge() argument
14182 EmitT32_32(0xff000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacge()
14192 EmitA32(0xf3000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacge()
14198 Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm); in vacge()
14202 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vacge() argument
14209 EmitT32_32(0xff000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacge()
14219 EmitA32(0xf3000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacge()
14225 Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm); in vacge()
14229 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vacgt() argument
14236 EmitT32_32(0xff200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacgt()
14246 EmitA32(0xf3200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacgt()
14252 Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm); in vacgt()
14256 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vacgt() argument
14263 EmitT32_32(0xff200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacgt()
14273 EmitA32(0xf3200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacgt()
14279 Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm); in vacgt()
14283 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vacle() argument
14290 EmitT32_32(0xff000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacle()
14300 EmitA32(0xf3000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacle()
14306 Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm); in vacle()
14310 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vacle() argument
14317 EmitT32_32(0xff000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacle()
14327 EmitA32(0xf3000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vacle()
14333 Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm); in vacle()
14337 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vaclt() argument
14344 EmitT32_32(0xff200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vaclt()
14354 EmitA32(0xf3200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vaclt()
14360 Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm); in vaclt()
14364 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vaclt() argument
14371 EmitT32_32(0xff200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vaclt()
14381 EmitA32(0xf3200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vaclt()
14387 Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm); in vaclt()
14391 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vadd() argument
14399 EmitT32_32(0xef000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vadd()
14407 EmitT32_32(0xee300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vadd()
14416 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vadd()
14425 EmitA32(0xf2000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vadd()
14433 rn.Encode(7, 16) | rm.Encode(5, 0)); in vadd()
14440 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vadd()
14445 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm); in vadd()
14449 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vadd() argument
14457 EmitT32_32(0xef000d40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vadd()
14467 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vadd()
14476 EmitA32(0xf2000d40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vadd()
14485 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vadd()
14490 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm); in vadd()
14494 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vadd() argument
14500 EmitT32_32(0xee300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vadd()
14509 rn.Encode(7, 16) | rm.Encode(5, 0)); in vadd()
14513 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm); in vadd()
14517 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vaddhn() argument
14526 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaddhn()
14536 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaddhn()
14541 Delegate(kVaddhn, &Assembler::vaddhn, cond, dt, rd, rn, rm); in vaddhn()
14545 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vaddl() argument
14555 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaddl()
14566 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaddl()
14571 Delegate(kVaddl, &Assembler::vaddl, cond, dt, rd, rn, rm); in vaddl()
14575 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { in vaddw() argument
14585 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaddw()
14596 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vaddw()
14601 Delegate(kVaddw, &Assembler::vaddw, cond, dt, rd, rn, rm); in vaddw()
14607 DRegister rn, in vand() argument
14615 if (encoded_dt.IsValid() && rd.Is(rn)) { in vand()
14628 if (encoded_dt.IsValid() && rd.Is(rn)) { in vand()
14645 EmitT32_32(0xef000110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vand()
14653 EmitA32(0xf2000110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vand()
14659 Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand); in vand()
14665 QRegister rn, in vand() argument
14673 if (encoded_dt.IsValid() && rd.Is(rn)) { in vand()
14686 if (encoded_dt.IsValid() && rd.Is(rn)) { in vand()
14703 EmitT32_32(0xef000150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vand()
14711 EmitA32(0xf2000150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vand()
14717 Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand); in vand()
14723 DRegister rn, in vbic() argument
14731 if (encoded_dt.IsValid() && rd.Is(rn)) { in vbic()
14744 if (encoded_dt.IsValid() && rd.Is(rn)) { in vbic()
14761 EmitT32_32(0xef100110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbic()
14769 EmitA32(0xf2100110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbic()
14775 Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand); in vbic()
14781 QRegister rn, in vbic() argument
14789 if (encoded_dt.IsValid() && rd.Is(rn)) { in vbic()
14802 if (encoded_dt.IsValid() && rd.Is(rn)) { in vbic()
14819 EmitT32_32(0xef100150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbic()
14827 EmitA32(0xf2100150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbic()
14833 Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand); in vbic()
14837 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vbif() argument
14844 EmitT32_32(0xff300110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbif()
14852 EmitA32(0xf3300110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbif()
14857 Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm); in vbif()
14861 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vbif() argument
14868 EmitT32_32(0xff300150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbif()
14876 EmitA32(0xf3300150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbif()
14881 Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm); in vbif()
14885 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vbit() argument
14892 EmitT32_32(0xff200110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbit()
14900 EmitA32(0xf3200110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbit()
14905 Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm); in vbit()
14909 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vbit() argument
14916 EmitT32_32(0xff200150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbit()
14924 EmitA32(0xf3200150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbit()
14929 Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm); in vbit()
14933 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vbsl() argument
14940 EmitT32_32(0xff100110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbsl()
14948 EmitA32(0xf3100110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbsl()
14953 Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm); in vbsl()
14957 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vbsl() argument
14964 EmitT32_32(0xff100150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbsl()
14972 EmitA32(0xf3100150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vbsl()
14977 Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm); in vbsl()
15061 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vceq() argument
15071 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15080 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15090 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15098 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15103 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm); in vceq()
15107 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vceq() argument
15117 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15126 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15136 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15144 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vceq()
15149 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm); in vceq()
15233 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vcge() argument
15243 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcge()
15251 EmitT32_32(0xff000e00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcge()
15263 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcge()
15270 EmitA32(0xf3000e00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcge()
15276 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm); in vcge()
15280 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vcge() argument
15290 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcge()
15298 EmitT32_32(0xff000e40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcge()
15310 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcge()
15317 EmitA32(0xf3000e40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcge()
15323 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm); in vcge()
15407 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vcgt() argument
15417 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcgt()
15425 EmitT32_32(0xff200e00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcgt()
15437 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcgt()
15444 EmitA32(0xf3200e00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcgt()
15450 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm); in vcgt()
15454 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vcgt() argument
15464 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcgt()
15472 EmitT32_32(0xff200e40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcgt()
15484 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vcgt()
15491 EmitA32(0xf3200e40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vcgt()
15497 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm); in vcgt()
15581 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vcle() argument
15591 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vcle()
15599 EmitT32_32(0xff000e00U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vcle()
15611 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vcle()
15618 EmitA32(0xf3000e00U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vcle()
15624 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm); in vcle()
15628 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vcle() argument
15638 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vcle()
15646 EmitT32_32(0xff000e40U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vcle()
15658 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vcle()
15665 EmitA32(0xf3000e40U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vcle()
15671 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm); in vcle()
15809 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vclt() argument
15819 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vclt()
15827 EmitT32_32(0xff200e00U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vclt()
15839 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vclt()
15846 EmitA32(0xf3200e00U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vclt()
15852 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm); in vclt()
15856 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vclt() argument
15866 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vclt()
15874 EmitT32_32(0xff200e40U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vclt()
15886 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16)); in vclt()
15893 EmitA32(0xf3200e40U | rd.Encode(22, 12) | rn.Encode(5, 0) | in vclt()
15899 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm); in vclt()
17229 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vdiv() argument
17235 EmitT32_32(0xee800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vdiv()
17244 rn.Encode(7, 16) | rm.Encode(5, 0)); in vdiv()
17248 Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm); in vdiv()
17252 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vdiv() argument
17258 EmitT32_32(0xee800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vdiv()
17267 rn.Encode(7, 16) | rm.Encode(5, 0)); in vdiv()
17271 Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm); in vdiv()
17397 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in veor() argument
17404 EmitT32_32(0xff000110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in veor()
17412 EmitA32(0xf3000110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in veor()
17417 Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm); in veor()
17421 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in veor() argument
17428 EmitT32_32(0xff000150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in veor()
17436 EmitA32(0xf3000150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in veor()
17441 Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm); in veor()
17447 DRegister rn, in vext() argument
17459 EmitT32_32(0xefb00000U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17470 EmitT32_32(0xefb00000U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17480 EmitA32(0xf2b00000U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17490 EmitA32(0xf2b00000U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17498 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand); in vext()
17504 QRegister rn, in vext() argument
17516 EmitT32_32(0xefb00040U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17527 EmitT32_32(0xefb00040U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17537 EmitA32(0xf2b00040U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17547 EmitA32(0xf2b00040U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vext()
17555 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand); in vext()
17559 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vfma() argument
17566 EmitT32_32(0xef000c10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfma()
17574 EmitT32_32(0xeea00b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfma()
17583 EmitA32(0xf2000c10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfma()
17591 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfma()
17595 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm); in vfma()
17599 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vfma() argument
17606 EmitT32_32(0xef000c50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfma()
17616 EmitA32(0xf2000c50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfma()
17622 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm); in vfma()
17626 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vfma() argument
17632 EmitT32_32(0xeea00a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfma()
17641 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfma()
17645 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm); in vfma()
17649 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vfms() argument
17656 EmitT32_32(0xef200c10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfms()
17664 EmitT32_32(0xeea00b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfms()
17673 EmitA32(0xf2200c10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfms()
17681 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfms()
17685 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm); in vfms()
17689 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vfms() argument
17696 EmitT32_32(0xef200c50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfms()
17706 EmitA32(0xf2200c50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfms()
17712 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm); in vfms()
17716 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vfms() argument
17722 EmitT32_32(0xeea00a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfms()
17731 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfms()
17735 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm); in vfms()
17739 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vfnma() argument
17745 EmitT32_32(0xee900a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfnma()
17754 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfnma()
17758 Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm); in vfnma()
17762 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vfnma() argument
17768 EmitT32_32(0xee900b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfnma()
17777 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfnma()
17781 Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm); in vfnma()
17785 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vfnms() argument
17791 EmitT32_32(0xee900a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfnms()
17800 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfnms()
17804 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm); in vfnms()
17808 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vfnms() argument
17814 EmitT32_32(0xee900b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vfnms()
17823 rn.Encode(7, 16) | rm.Encode(5, 0)); in vfnms()
17827 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm); in vfnms()
17831 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vhadd() argument
17841 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhadd()
17852 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhadd()
17857 Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm); in vhadd()
17861 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vhadd() argument
17871 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhadd()
17882 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhadd()
17887 Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm); in vhadd()
17891 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vhsub() argument
17901 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhsub()
17912 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhsub()
17917 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm); in vhsub()
17921 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vhsub() argument
17931 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhsub()
17942 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vhsub()
17947 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm); in vhsub()
17957 Register rn = operand.GetBaseRegister(); in vld1() local
17969 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
17992 (rn.GetCode() << 16)); in vld1()
18001 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18024 (rn.GetCode() << 16)); in vld1()
18033 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18040 (rn.GetCode() << 16)); in vld1()
18049 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18056 (rn.GetCode() << 16)); in vld1()
18064 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18069 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld1()
18077 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18082 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld1()
18092 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18115 (rn.GetCode() << 16)); in vld1()
18123 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18146 (rn.GetCode() << 16)); in vld1()
18154 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18161 (rn.GetCode() << 16)); in vld1()
18169 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18176 (rn.GetCode() << 16)); in vld1()
18183 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18188 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld1()
18195 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18200 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld1()
18207 Register rn = operand.GetBaseRegister(); in vld1() local
18219 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18242 (rn.GetCode() << 16) | rm.GetCode()); in vld1()
18250 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18257 (rn.GetCode() << 16) | rm.GetCode()); in vld1()
18265 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18270 first.Encode(22, 12) | (rn.GetCode() << 16) | in vld1()
18280 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18303 (rn.GetCode() << 16) | rm.GetCode()); in vld1()
18310 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18317 (rn.GetCode() << 16) | rm.GetCode()); in vld1()
18324 (!rn.IsPC() || AllowUnpredictable())) { in vld1()
18329 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vld1()
18345 Register rn = operand.GetBaseRegister(); in vld2() local
18358 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18374 (rn.GetCode() << 16)); in vld2()
18385 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18401 (rn.GetCode() << 16)); in vld2()
18411 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18418 (rn.GetCode() << 16)); in vld2()
18428 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18435 (rn.GetCode() << 16)); in vld2()
18445 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18450 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld2()
18460 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18465 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld2()
18477 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18493 (rn.GetCode() << 16)); in vld2()
18503 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18519 (rn.GetCode() << 16)); in vld2()
18528 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18535 (rn.GetCode() << 16)); in vld2()
18544 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18551 (rn.GetCode() << 16)); in vld2()
18560 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18565 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld2()
18574 (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18579 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld2()
18586 Register rn = operand.GetBaseRegister(); in vld2() local
18599 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18615 (rn.GetCode() << 16) | rm.GetCode()); in vld2()
18624 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18631 (rn.GetCode() << 16) | rm.GetCode()); in vld2()
18640 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18645 first.Encode(22, 12) | (rn.GetCode() << 16) | in vld2()
18657 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18673 (rn.GetCode() << 16) | rm.GetCode()); in vld2()
18681 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18688 (rn.GetCode() << 16) | rm.GetCode()); in vld2()
18696 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()
18701 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vld2()
18717 Register rn = operand.GetBaseRegister(); in vld3() local
18727 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18734 (rn.GetCode() << 16)); in vld3()
18744 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18751 (rn.GetCode() << 16)); in vld3()
18762 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18769 (rn.GetCode() << 16)); in vld3()
18778 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18785 (rn.GetCode() << 16)); in vld3()
18792 Register rn = operand.GetBaseRegister(); in vld3() local
18802 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18809 (rn.GetCode() << 16) | rm.GetCode()); in vld3()
18819 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18826 (rn.GetCode() << 16) | rm.GetCode()); in vld3()
18842 Register rn = operand.GetBaseRegister(); in vld3() local
18850 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18856 (rn.GetCode() << 16)); in vld3()
18865 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18871 (rn.GetCode() << 16)); in vld3()
18880 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18885 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld3()
18894 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18899 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld3()
18909 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18915 (rn.GetCode() << 16)); in vld3()
18923 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18929 (rn.GetCode() << 16)); in vld3()
18937 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18942 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld3()
18950 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18955 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld3()
18962 Register rn = operand.GetBaseRegister(); in vld3() local
18973 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18979 (rn.GetCode() << 16) | rm.GetCode()); in vld3()
18989 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
18994 first.Encode(22, 12) | (rn.GetCode() << 16) | in vld3()
19006 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
19012 (rn.GetCode() << 16) | rm.GetCode()); in vld3()
19021 (!rn.IsPC() || AllowUnpredictable())) { in vld3()
19026 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vld3()
19042 Register rn = operand.GetBaseRegister(); in vld4() local
19055 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19062 (rn.GetCode() << 16)); in vld4()
19072 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19079 (rn.GetCode() << 16)); in vld4()
19089 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19096 (rn.GetCode() << 16)); in vld4()
19106 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19113 (rn.GetCode() << 16)); in vld4()
19123 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19128 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld4()
19138 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19143 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld4()
19154 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19161 (rn.GetCode() << 16)); in vld4()
19170 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19177 (rn.GetCode() << 16)); in vld4()
19186 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19193 (rn.GetCode() << 16)); in vld4()
19202 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19209 (rn.GetCode() << 16)); in vld4()
19218 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19223 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld4()
19232 (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19237 first.Encode(22, 12) | (rn.GetCode() << 16)); in vld4()
19244 Register rn = operand.GetBaseRegister(); in vld4() local
19257 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19264 (rn.GetCode() << 16) | rm.GetCode()); in vld4()
19273 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19280 (rn.GetCode() << 16) | rm.GetCode()); in vld4()
19289 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19294 first.Encode(22, 12) | (rn.GetCode() << 16) | in vld4()
19305 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19312 (rn.GetCode() << 16) | rm.GetCode()); in vld4()
19320 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19327 (rn.GetCode() << 16) | rm.GetCode()); in vld4()
19335 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld4()
19340 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vld4()
19351 Register rn, in vldm() argument
19359 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vldm()
19363 EmitT32_32(0xec900b00U | (rn.GetCode() << 16) | in vldm()
19372 (!rn.IsPC() || !write_back.DoesWriteBack())) || in vldm()
19376 EmitA32(0x0c900b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vldm()
19382 Delegate(kVldm, &Assembler::vldm, cond, dt, rn, write_back, dreglist); in vldm()
19387 Register rn, in vldm() argument
19395 if ((!rn.IsPC() || AllowUnpredictable())) { in vldm()
19398 EmitT32_32(0xec900a00U | (rn.GetCode() << 16) | in vldm()
19407 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) { in vldm()
19410 EmitA32(0x0c900a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vldm()
19416 Delegate(kVldm, &Assembler::vldm, cond, dt, rn, write_back, sreglist); in vldm()
19421 Register rn, in vldmdb() argument
19430 (((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vldmdb()
19434 EmitT32_32(0xed300b00U | (rn.GetCode() << 16) | dreg.Encode(22, 12) | in vldmdb()
19442 (((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vldmdb()
19446 EmitA32(0x0d300b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vldmdb()
19451 Delegate(kVldmdb, &Assembler::vldmdb, cond, dt, rn, write_back, dreglist); in vldmdb()
19456 Register rn, in vldmdb() argument
19464 if (write_back.DoesWriteBack() && (!rn.IsPC() || AllowUnpredictable())) { in vldmdb()
19467 EmitT32_32(0xed300a00U | (rn.GetCode() << 16) | sreg.Encode(22, 12) | in vldmdb()
19475 (!rn.IsPC() || AllowUnpredictable())) { in vldmdb()
19478 EmitA32(0x0d300a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vldmdb()
19483 Delegate(kVldmdb, &Assembler::vldmdb, cond, dt, rn, write_back, sreglist); in vldmdb()
19488 Register rn, in vldmia() argument
19496 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vldmia()
19500 EmitT32_32(0xec900b00U | (rn.GetCode() << 16) | in vldmia()
19509 (!rn.IsPC() || !write_back.DoesWriteBack())) || in vldmia()
19513 EmitA32(0x0c900b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vldmia()
19519 Delegate(kVldmia, &Assembler::vldmia, cond, dt, rn, write_back, dreglist); in vldmia()
19524 Register rn, in vldmia() argument
19532 if ((!rn.IsPC() || AllowUnpredictable())) { in vldmia()
19535 EmitT32_32(0xec900a00U | (rn.GetCode() << 16) | in vldmia()
19544 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) { in vldmia()
19547 EmitA32(0x0c900a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vldmia()
19553 Delegate(kVldmia, &Assembler::vldmia, cond, dt, rn, write_back, sreglist); in vldmia()
19661 Register rn = operand.GetBaseRegister(); in vldr() local
19666 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset()) { in vldr()
19676 ((rn.GetCode() & 0xf) != 0xf)) { in vldr()
19679 EmitT32_32(0xed100b00U | rd.Encode(22, 12) | (rn.GetCode() << 16) | in vldr()
19687 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset() && in vldr()
19698 ((rn.GetCode() & 0xf) != 0xf)) { in vldr()
19702 (rn.GetCode() << 16) | offset_ | (sign << 23)); in vldr()
19815 Register rn = operand.GetBaseRegister(); in vldr() local
19820 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset()) { in vldr()
19830 ((rn.GetCode() & 0xf) != 0xf)) { in vldr()
19833 EmitT32_32(0xed100a00U | rd.Encode(22, 12) | (rn.GetCode() << 16) | in vldr()
19841 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset() && in vldr()
19852 ((rn.GetCode() & 0xf) != 0xf)) { in vldr()
19856 (rn.GetCode() << 16) | offset_ | (sign << 23)); in vldr()
19865 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vmax() argument
19873 EmitT32_32(0xef000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmax()
19884 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmax()
19893 EmitA32(0xf2000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmax()
19903 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmax()
19908 Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm); in vmax()
19912 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vmax() argument
19920 EmitT32_32(0xef000f40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmax()
19931 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmax()
19940 EmitA32(0xf2000f40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmax()
19950 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmax()
19955 Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm); in vmax()
19958 void Assembler::vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vmaxnm() argument
19964 EmitT32_32(0xff000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
19971 EmitT32_32(0xfe800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
19979 EmitA32(0xf3000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
19985 EmitA32(0xfe800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
19990 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm); in vmaxnm()
19993 void Assembler::vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vmaxnm() argument
19999 EmitT32_32(0xff000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
20007 EmitA32(0xf3000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
20012 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm); in vmaxnm()
20015 void Assembler::vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vmaxnm() argument
20021 EmitT32_32(0xfe800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
20029 EmitA32(0xfe800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmaxnm()
20034 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm); in vmaxnm()
20038 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vmin() argument
20046 EmitT32_32(0xef200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmin()
20057 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmin()
20066 EmitA32(0xf2200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmin()
20076 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmin()
20081 Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm); in vmin()
20085 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vmin() argument
20093 EmitT32_32(0xef200f40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmin()
20104 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmin()
20113 EmitA32(0xf2200f40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmin()
20123 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmin()
20128 Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm); in vmin()
20131 void Assembler::vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vminnm() argument
20137 EmitT32_32(0xff200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20144 EmitT32_32(0xfe800b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20152 EmitA32(0xf3200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20158 EmitA32(0xfe800b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20163 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm); in vminnm()
20166 void Assembler::vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vminnm() argument
20172 EmitT32_32(0xff200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20180 EmitA32(0xf3200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20185 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm); in vminnm()
20188 void Assembler::vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vminnm() argument
20194 EmitT32_32(0xfe800a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20202 EmitA32(0xfe800a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vminnm()
20207 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm); in vminnm()
20211 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { in vmla() argument
20224 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmla()
20238 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmla()
20243 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm); in vmla()
20247 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { in vmla() argument
20260 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmla()
20274 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmla()
20279 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm); in vmla()
20283 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vmla() argument
20291 EmitT32_32(0xef000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmla()
20299 EmitT32_32(0xee000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmla()
20308 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmla()
20317 EmitA32(0xf2000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmla()
20325 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmla()
20332 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmla()
20337 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm); in vmla()
20341 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vmla() argument
20349 EmitT32_32(0xef000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmla()
20359 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmla()
20368 EmitA32(0xf2000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmla()
20377 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmla()
20382 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm); in vmla()
20386 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vmla() argument
20392 EmitT32_32(0xee000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmla()
20401 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmla()
20405 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm); in vmla()
20409 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { in vmlal() argument
20422 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmlal()
20436 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmlal()
20441 Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm); in vmlal()
20445 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vmlal() argument
20455 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmlal()
20466 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmlal()
20471 Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm); in vmlal()
20475 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { in vmls() argument
20488 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmls()
20502 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmls()
20507 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm); in vmls()
20511 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { in vmls() argument
20524 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmls()
20538 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmls()
20543 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm); in vmls()
20547 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vmls() argument
20555 EmitT32_32(0xef200d10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmls()
20563 EmitT32_32(0xee000b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmls()
20572 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmls()
20581 EmitA32(0xf2200d10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmls()
20589 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmls()
20596 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmls()
20601 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm); in vmls()
20605 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vmls() argument
20613 EmitT32_32(0xef200d50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmls()
20623 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmls()
20632 EmitA32(0xf2200d50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmls()
20641 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmls()
20646 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm); in vmls()
20650 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vmls() argument
20656 EmitT32_32(0xee000a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmls()
20665 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmls()
20669 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm); in vmls()
20673 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { in vmlsl() argument
20686 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmlsl()
20700 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vmlsl()
20705 Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm); in vmlsl()
20709 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vmlsl() argument
20719 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmlsl()
20730 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmlsl()
20735 Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm); in vmlsl()
20738 void Assembler::vmov(Condition cond, Register rt, SRegister rn) { in vmov() argument
20744 EmitT32_32(0xee100a10U | (rt.GetCode() << 12) | rn.Encode(7, 16)); in vmov()
20752 rn.Encode(7, 16)); in vmov()
20756 Delegate(kVmov, &Assembler::vmov, cond, rt, rn); in vmov()
20759 void Assembler::vmov(Condition cond, SRegister rn, Register rt) { in vmov() argument
20765 EmitT32_32(0xee000a10U | rn.Encode(7, 16) | (rt.GetCode() << 12)); in vmov()
20772 EmitA32(0x0e000a10U | (cond.GetCondition() << 28) | rn.Encode(7, 16) | in vmov()
20777 Delegate(kVmov, &Assembler::vmov, cond, rn, rt); in vmov()
21116 DRegisterLane rn) { in vmov() argument
21119 Dt_U_opc1_opc2_1 encoded_dt(dt, rn); in vmov()
21126 (rt.GetCode() << 12) | rn.Encode(7, 16)); in vmov()
21138 (rt.GetCode() << 12) | rn.Encode(7, 16)); in vmov()
21142 Delegate(kVmov, &Assembler::vmov, cond, dt, rt, rn); in vmov()
21247 DRegister rn, in vmul() argument
21266 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vmul()
21285 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vmul()
21291 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, dm, index); in vmul()
21297 QRegister rn, in vmul() argument
21316 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vmul()
21335 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vmul()
21341 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, dm, index); in vmul()
21345 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vmul() argument
21353 EmitT32_32(0xff000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmul()
21361 EmitT32_32(0xee200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmul()
21371 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmul()
21380 EmitA32(0xf3000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmul()
21388 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmul()
21396 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmul()
21401 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm); in vmul()
21405 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vmul() argument
21413 EmitT32_32(0xff000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmul()
21424 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmul()
21433 EmitA32(0xf3000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmul()
21443 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmul()
21448 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm); in vmul()
21452 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vmul() argument
21458 EmitT32_32(0xee200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vmul()
21467 rn.Encode(7, 16) | rm.Encode(5, 0)); in vmul()
21471 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm); in vmul()
21477 DRegister rn, in vmull() argument
21497 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vmull()
21517 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vmull()
21523 Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, dm, index); in vmull()
21527 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vmull() argument
21538 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmull()
21550 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vmull()
21555 Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, rm); in vmull()
21760 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vnmla() argument
21766 EmitT32_32(0xee100a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vnmla()
21775 rn.Encode(7, 16) | rm.Encode(5, 0)); in vnmla()
21779 Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm); in vnmla()
21783 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vnmla() argument
21789 EmitT32_32(0xee100b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vnmla()
21798 rn.Encode(7, 16) | rm.Encode(5, 0)); in vnmla()
21802 Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm); in vnmla()
21806 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vnmls() argument
21812 EmitT32_32(0xee100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vnmls()
21821 rn.Encode(7, 16) | rm.Encode(5, 0)); in vnmls()
21825 Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm); in vnmls()
21829 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vnmls() argument
21835 EmitT32_32(0xee100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vnmls()
21844 rn.Encode(7, 16) | rm.Encode(5, 0)); in vnmls()
21848 Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm); in vnmls()
21852 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vnmul() argument
21858 EmitT32_32(0xee200a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vnmul()
21867 rn.Encode(7, 16) | rm.Encode(5, 0)); in vnmul()
21871 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm); in vnmul()
21875 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vnmul() argument
21881 EmitT32_32(0xee200b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vnmul()
21890 rn.Encode(7, 16) | rm.Encode(5, 0)); in vnmul()
21894 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm); in vnmul()
21900 DRegister rn, in vorn() argument
21908 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorn()
21921 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorn()
21938 EmitT32_32(0xef300110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorn()
21946 EmitA32(0xf2300110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorn()
21952 Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand); in vorn()
21958 QRegister rn, in vorn() argument
21966 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorn()
21979 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorn()
21996 EmitT32_32(0xef300150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorn()
22004 EmitA32(0xf2300150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorn()
22010 Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand); in vorn()
22016 DRegister rn, in vorr() argument
22026 EmitT32_32(0xef200110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorr()
22034 EmitA32(0xf2200110U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorr()
22044 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorr()
22057 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorr()
22068 Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand); in vorr()
22074 QRegister rn, in vorr() argument
22084 EmitT32_32(0xef200150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorr()
22092 EmitA32(0xf2200150U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vorr()
22102 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorr()
22115 if (encoded_dt.IsValid() && rd.Is(rn)) { in vorr()
22126 Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand); in vorr()
22194 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vpadd() argument
22202 EmitT32_32(0xff000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vpadd()
22212 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vpadd()
22221 EmitA32(0xf3000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vpadd()
22230 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vpadd()
22235 Delegate(kVpadd, &Assembler::vpadd, cond, dt, rd, rn, rm); in vpadd()
22303 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vpmax() argument
22311 EmitT32_32(0xff000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vpmax()
22322 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vpmax()
22331 EmitA32(0xf3000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vpmax()
22341 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vpmax()
22346 Delegate(kVpmax, &Assembler::vpmax, cond, dt, rd, rn, rm); in vpmax()
22350 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vpmin() argument
22358 EmitT32_32(0xff200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vpmin()
22369 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vpmin()
22378 EmitA32(0xf3200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vpmin()
22388 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vpmin()
22393 Delegate(kVpmin, &Assembler::vpmin, cond, dt, rd, rn, rm); in vpmin()
22553 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vqadd() argument
22563 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqadd()
22574 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqadd()
22579 Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm); in vqadd()
22583 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vqadd() argument
22593 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqadd()
22604 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqadd()
22609 Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm); in vqadd()
22613 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vqdmlal() argument
22622 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmlal()
22632 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmlal()
22637 Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, rm); in vqdmlal()
22643 DRegister rn, in vqdmlal() argument
22662 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vqdmlal()
22681 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vqdmlal()
22687 Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, dm, index); in vqdmlal()
22691 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vqdmlsl() argument
22700 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmlsl()
22710 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmlsl()
22715 Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, rm); in vqdmlsl()
22721 DRegister rn, in vqdmlsl() argument
22740 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vqdmlsl()
22759 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) | in vqdmlsl()
22765 Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, dm, index); in vqdmlsl()
22769 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vqdmulh() argument
22778 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmulh()
22788 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmulh()
22793 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
22797 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vqdmulh() argument
22806 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmulh()
22816 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmulh()
22821 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
22825 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { in vqdmulh() argument
22838 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqdmulh()
22852 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqdmulh()
22857 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
22861 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { in vqdmulh() argument
22874 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqdmulh()
22888 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqdmulh()
22893 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
22897 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vqdmull() argument
22906 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmull()
22916 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqdmull()
22921 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm); in vqdmull()
22925 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { in vqdmull() argument
22938 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqdmull()
22952 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqdmull()
22957 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm); in vqdmull()
23077 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vqrdmulh() argument
23086 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqrdmulh()
23096 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqrdmulh()
23101 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm); in vqrdmulh()
23105 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vqrdmulh() argument
23114 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqrdmulh()
23124 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqrdmulh()
23129 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm); in vqrdmulh()
23133 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { in vqrdmulh() argument
23146 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqrdmulh()
23160 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqrdmulh()
23165 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm); in vqrdmulh()
23169 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { in vqrdmulh() argument
23182 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqrdmulh()
23196 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0)); in vqrdmulh()
23201 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm); in vqrdmulh()
23205 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { in vqrshl() argument
23215 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqrshl()
23226 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqrshl()
23231 Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn); in vqrshl()
23235 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { in vqrshl() argument
23245 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqrshl()
23256 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqrshl()
23261 Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn); in vqrshl()
23393 DRegister rn = operand.GetRegister(); in vqshl() local
23402 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqshl()
23413 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqshl()
23462 QRegister rn = operand.GetRegister(); in vqshl() local
23471 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqshl()
23482 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vqshl()
23729 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vqsub() argument
23739 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqsub()
23750 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqsub()
23755 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm); in vqsub()
23759 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vqsub() argument
23769 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqsub()
23780 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vqsub()
23785 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm); in vqsub()
23789 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vraddhn() argument
23798 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vraddhn()
23808 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vraddhn()
23813 Delegate(kVraddhn, &Assembler::vraddhn, cond, dt, rd, rn, rm); in vraddhn()
23881 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vrecps() argument
23888 EmitT32_32(0xef000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrecps()
23898 EmitA32(0xf2000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrecps()
23904 Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm); in vrecps()
23908 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vrecps() argument
23915 EmitT32_32(0xef000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrecps()
23925 EmitA32(0xf2000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrecps()
23931 Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm); in vrecps()
24115 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vrhadd() argument
24125 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vrhadd()
24136 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vrhadd()
24141 Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm); in vrhadd()
24145 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vrhadd() argument
24155 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vrhadd()
24166 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vrhadd()
24171 Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm); in vrhadd()
24653 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { in vrshl() argument
24663 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vrshl()
24674 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vrshl()
24679 Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn); in vrshl()
24683 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { in vrshl() argument
24693 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vrshl()
24704 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vrshl()
24709 Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn); in vrshl()
24953 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vrsqrts() argument
24960 EmitT32_32(0xef200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrsqrts()
24970 EmitA32(0xf2200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrsqrts()
24976 Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm); in vrsqrts()
24980 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vrsqrts() argument
24987 EmitT32_32(0xef200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrsqrts()
24997 EmitA32(0xf2200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vrsqrts()
25003 Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm); in vrsqrts()
25091 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vrsubhn() argument
25100 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vrsubhn()
25110 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vrsubhn()
25115 Delegate(kVrsubhn, &Assembler::vrsubhn, cond, dt, rd, rn, rm); in vrsubhn()
25118 void Assembler::vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vseleq() argument
25124 EmitT32_32(0xfe000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vseleq()
25132 EmitA32(0xfe000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vseleq()
25137 Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm); in vseleq()
25140 void Assembler::vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vseleq() argument
25146 EmitT32_32(0xfe000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vseleq()
25154 EmitA32(0xfe000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vseleq()
25159 Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm); in vseleq()
25162 void Assembler::vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vselge() argument
25168 EmitT32_32(0xfe200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselge()
25176 EmitA32(0xfe200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselge()
25181 Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm); in vselge()
25184 void Assembler::vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vselge() argument
25190 EmitT32_32(0xfe200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselge()
25198 EmitA32(0xfe200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselge()
25203 Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm); in vselge()
25206 void Assembler::vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vselgt() argument
25212 EmitT32_32(0xfe300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselgt()
25220 EmitA32(0xfe300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselgt()
25225 Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm); in vselgt()
25228 void Assembler::vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vselgt() argument
25234 EmitT32_32(0xfe300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselgt()
25242 EmitA32(0xfe300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselgt()
25247 Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm); in vselgt()
25250 void Assembler::vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vselvs() argument
25256 EmitT32_32(0xfe100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselvs()
25264 EmitA32(0xfe100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselvs()
25269 Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm); in vselvs()
25272 void Assembler::vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vselvs() argument
25278 EmitT32_32(0xfe100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselvs()
25286 EmitA32(0xfe100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vselvs()
25291 Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm); in vselvs()
25334 DRegister rn = operand.GetRegister(); in vshl() local
25343 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vshl()
25354 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vshl()
25403 QRegister rn = operand.GetRegister(); in vshl() local
25412 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vshl()
25423 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16)); in vshl()
25967 Register rn = operand.GetBaseRegister(); in vst1() local
25978 (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26001 (rn.GetCode() << 16)); in vst1()
26010 (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26033 (rn.GetCode() << 16)); in vst1()
26041 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26046 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst1()
26054 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26059 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst1()
26069 (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26092 (rn.GetCode() << 16)); in vst1()
26100 (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26123 (rn.GetCode() << 16)); in vst1()
26130 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26135 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst1()
26142 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26147 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst1()
26154 Register rn = operand.GetBaseRegister(); in vst1() local
26165 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26188 (rn.GetCode() << 16) | rm.GetCode()); in vst1()
26196 (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26201 first.Encode(22, 12) | (rn.GetCode() << 16) | in vst1()
26211 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26234 (rn.GetCode() << 16) | rm.GetCode()); in vst1()
26241 (!rn.IsPC() || AllowUnpredictable())) { in vst1()
26246 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vst1()
26262 Register rn = operand.GetBaseRegister(); in vst2() local
26274 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26290 (rn.GetCode() << 16)); in vst2()
26301 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26317 (rn.GetCode() << 16)); in vst2()
26327 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26332 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst2()
26342 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26347 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst2()
26359 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26375 (rn.GetCode() << 16)); in vst2()
26385 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26401 (rn.GetCode() << 16)); in vst2()
26410 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26415 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst2()
26424 (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26429 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst2()
26436 Register rn = operand.GetBaseRegister(); in vst2() local
26448 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26464 (rn.GetCode() << 16) | rm.GetCode()); in vst2()
26473 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26478 first.Encode(22, 12) | (rn.GetCode() << 16) | in vst2()
26490 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26506 (rn.GetCode() << 16) | rm.GetCode()); in vst2()
26514 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst2()
26519 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vst2()
26535 Register rn = operand.GetBaseRegister(); in vst3() local
26545 (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26552 (rn.GetCode() << 16)); in vst3()
26562 (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26569 (rn.GetCode() << 16)); in vst3()
26580 (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26587 (rn.GetCode() << 16)); in vst3()
26596 (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26603 (rn.GetCode() << 16)); in vst3()
26610 Register rn = operand.GetBaseRegister(); in vst3() local
26620 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26627 (rn.GetCode() << 16) | rm.GetCode()); in vst3()
26637 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26644 (rn.GetCode() << 16) | rm.GetCode()); in vst3()
26660 Register rn = operand.GetBaseRegister(); in vst3() local
26668 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26673 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst3()
26682 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26687 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst3()
26697 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26702 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst3()
26710 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26715 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst3()
26722 Register rn = operand.GetBaseRegister(); in vst3() local
26733 (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26738 first.Encode(22, 12) | (rn.GetCode() << 16) | in vst3()
26750 (!rn.IsPC() || AllowUnpredictable())) { in vst3()
26755 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vst3()
26771 Register rn = operand.GetBaseRegister(); in vst4() local
26782 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26789 (rn.GetCode() << 16)); in vst4()
26799 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26806 (rn.GetCode() << 16)); in vst4()
26816 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26821 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst4()
26831 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26836 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst4()
26847 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26854 (rn.GetCode() << 16)); in vst4()
26863 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26870 (rn.GetCode() << 16)); in vst4()
26879 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26884 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst4()
26893 (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26898 first.Encode(22, 12) | (rn.GetCode() << 16)); in vst4()
26905 Register rn = operand.GetBaseRegister(); in vst4() local
26916 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26923 (rn.GetCode() << 16) | rm.GetCode()); in vst4()
26932 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26937 first.Encode(22, 12) | (rn.GetCode() << 16) | in vst4()
26948 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26955 (rn.GetCode() << 16) | rm.GetCode()); in vst4()
26963 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vst4()
26968 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode()); in vst4()
26979 Register rn, in vstm() argument
26987 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vstm()
26991 EmitT32_32(0xec800b00U | (rn.GetCode() << 16) | in vstm()
27000 (!rn.IsPC() || !write_back.DoesWriteBack())) || in vstm()
27004 EmitA32(0x0c800b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vstm()
27010 Delegate(kVstm, &Assembler::vstm, cond, dt, rn, write_back, dreglist); in vstm()
27015 Register rn, in vstm() argument
27023 if ((!rn.IsPC() || AllowUnpredictable())) { in vstm()
27026 EmitT32_32(0xec800a00U | (rn.GetCode() << 16) | in vstm()
27035 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) { in vstm()
27038 EmitA32(0x0c800a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vstm()
27044 Delegate(kVstm, &Assembler::vstm, cond, dt, rn, write_back, sreglist); in vstm()
27049 Register rn, in vstmdb() argument
27058 (((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vstmdb()
27062 EmitT32_32(0xed200b00U | (rn.GetCode() << 16) | dreg.Encode(22, 12) | in vstmdb()
27070 (((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vstmdb()
27074 EmitA32(0x0d200b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vstmdb()
27079 Delegate(kVstmdb, &Assembler::vstmdb, cond, dt, rn, write_back, dreglist); in vstmdb()
27084 Register rn, in vstmdb() argument
27092 if (write_back.DoesWriteBack() && (!rn.IsPC() || AllowUnpredictable())) { in vstmdb()
27095 EmitT32_32(0xed200a00U | (rn.GetCode() << 16) | sreg.Encode(22, 12) | in vstmdb()
27103 (!rn.IsPC() || AllowUnpredictable())) { in vstmdb()
27106 EmitA32(0x0d200a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vstmdb()
27111 Delegate(kVstmdb, &Assembler::vstmdb, cond, dt, rn, write_back, sreglist); in vstmdb()
27116 Register rn, in vstmia() argument
27124 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) || in vstmia()
27128 EmitT32_32(0xec800b00U | (rn.GetCode() << 16) | in vstmia()
27137 (!rn.IsPC() || !write_back.DoesWriteBack())) || in vstmia()
27141 EmitA32(0x0c800b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vstmia()
27147 Delegate(kVstmia, &Assembler::vstmia, cond, dt, rn, write_back, dreglist); in vstmia()
27152 Register rn, in vstmia() argument
27160 if ((!rn.IsPC() || AllowUnpredictable())) { in vstmia()
27163 EmitT32_32(0xec800a00U | (rn.GetCode() << 16) | in vstmia()
27172 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) { in vstmia()
27175 EmitA32(0x0c800a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) | in vstmia()
27181 Delegate(kVstmia, &Assembler::vstmia, cond, dt, rn, write_back, sreglist); in vstmia()
27191 Register rn = operand.GetBaseRegister(); in vstr() local
27197 (!rn.IsPC() || AllowUnpredictable())) { in vstr()
27200 EmitT32_32(0xed000b00U | rd.Encode(22, 12) | (rn.GetCode() << 16) | in vstr()
27212 (rn.GetCode() << 16) | offset_ | (sign << 23)); in vstr()
27227 Register rn = operand.GetBaseRegister(); in vstr() local
27233 (!rn.IsPC() || AllowUnpredictable())) { in vstr()
27236 EmitT32_32(0xed000a00U | rd.Encode(22, 12) | (rn.GetCode() << 16) | in vstr()
27248 (rn.GetCode() << 16) | offset_ | (sign << 23)); in vstr()
27257 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vsub() argument
27265 EmitT32_32(0xef200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vsub()
27273 EmitT32_32(0xee300b40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vsub()
27282 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsub()
27291 EmitA32(0xf2200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vsub()
27299 rn.Encode(7, 16) | rm.Encode(5, 0)); in vsub()
27306 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsub()
27311 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm); in vsub()
27315 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vsub() argument
27323 EmitT32_32(0xef200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vsub()
27333 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsub()
27342 EmitA32(0xf2200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vsub()
27351 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsub()
27356 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm); in vsub()
27360 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { in vsub() argument
27366 EmitT32_32(0xee300a40U | rd.Encode(22, 12) | rn.Encode(7, 16) | in vsub()
27375 rn.Encode(7, 16) | rm.Encode(5, 0)); in vsub()
27379 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm); in vsub()
27383 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vsubhn() argument
27392 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsubhn()
27402 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsubhn()
27407 Delegate(kVsubhn, &Assembler::vsubhn, cond, dt, rd, rn, rm); in vsubhn()
27411 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vsubl() argument
27421 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsubl()
27432 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsubl()
27437 Delegate(kVsubl, &Assembler::vsubl, cond, dt, rd, rn, rm); in vsubl()
27441 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { in vsubw() argument
27451 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsubw()
27462 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vsubw()
27467 Delegate(kVsubw, &Assembler::vsubw, cond, dt, rd, rn, rm); in vsubw()
27639 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vtst() argument
27648 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vtst()
27658 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vtst()
27663 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm); in vtst()
27667 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vtst() argument
27676 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vtst()
27686 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0)); in vtst()
27691 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm); in vtst()