Lines Matching refs:rn
731 const Register& rn, in And() argument
734 LogicalMacro(rd, rn, operand, AND); in And()
739 const Register& rn, in Ands() argument
742 LogicalMacro(rd, rn, operand, ANDS); in Ands()
746 void MacroAssembler::Tst(const Register& rn, const Operand& operand) { in Tst() argument
748 Ands(AppropriateZeroRegFor(rn), rn, operand); in Tst()
753 const Register& rn, in Bic() argument
756 LogicalMacro(rd, rn, operand, BIC); in Bic()
761 const Register& rn, in Bics() argument
764 LogicalMacro(rd, rn, operand, BICS); in Bics()
769 const Register& rn, in Orr() argument
772 LogicalMacro(rd, rn, operand, ORR); in Orr()
777 const Register& rn, in Orn() argument
780 LogicalMacro(rd, rn, operand, ORN); in Orn()
785 const Register& rn, in Eor() argument
788 LogicalMacro(rd, rn, operand, EOR); in Eor()
793 const Register& rn, in Eon() argument
796 LogicalMacro(rd, rn, operand, EON); in Eon()
801 const Register& rn, in LogicalMacro() argument
840 Mov(rd, rn); in LogicalMacro()
853 Mov(rd, rn); in LogicalMacro()
859 Mvn(rd, rn); in LogicalMacro()
873 LogicalImmediate(rd, rn, n, imm_s, imm_r, op); in LogicalMacro()
876 Register temp = temps.AcquireSameSizeAs(rn); in LogicalMacro()
880 PreShiftImmMode mode = rn.IsSP() ? kNoShift : kAnyShift; in LogicalMacro()
886 Logical(temp, rn, imm_operand, op); in LogicalMacro()
889 Logical(rd, rn, imm_operand, op); in LogicalMacro()
902 Register temp = temps.AcquireSameSizeAs(rn); in LogicalMacro()
907 Logical(rd, rn, Operand(temp), op); in LogicalMacro()
911 Logical(rd, rn, operand, op); in LogicalMacro()
1155 void MacroAssembler::Ccmp(const Register& rn, in Ccmp() argument
1161 ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMN); in Ccmp()
1163 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP); in Ccmp()
1168 void MacroAssembler::Ccmn(const Register& rn, in Ccmn() argument
1174 ConditionalCompareMacro(rn, -operand.GetImmediate(), nzcv, cond, CCMP); in Ccmn()
1176 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN); in Ccmn()
1181 void MacroAssembler::ConditionalCompareMacro(const Register& rn, in ConditionalCompareMacro() argument
1197 ConditionalCompare(rn, operand, nzcv, cond, op); in ConditionalCompareMacro()
1202 Register temp = temps.AcquireSameSizeAs(rn); in ConditionalCompareMacro()
1204 ConditionalCompare(rn, temp, nzcv, cond, op); in ConditionalCompareMacro()
1405 const Register& rn, in Add() argument
1411 AddSubMacro(rd, rn, -operand.GetImmediate(), S, SUB); in Add()
1413 AddSubMacro(rd, rn, operand, S, ADD); in Add()
1419 const Register& rn, in Adds() argument
1421 Add(rd, rn, operand, SetFlags); in Adds()
1426 const Register& rn, in Sub() argument
1432 AddSubMacro(rd, rn, -operand.GetImmediate(), S, ADD); in Sub()
1434 AddSubMacro(rd, rn, operand, S, SUB); in Sub()
1440 const Register& rn, in Subs() argument
1442 Sub(rd, rn, operand, SetFlags); in Subs()
1446 void MacroAssembler::Cmn(const Register& rn, const Operand& operand) { in Cmn() argument
1448 Adds(AppropriateZeroRegFor(rn), rn, operand); in Cmn()
1452 void MacroAssembler::Cmp(const Register& rn, const Operand& operand) { in Cmp() argument
1454 Subs(AppropriateZeroRegFor(rn), rn, operand); in Cmp()
1679 const Register& rn, in AddSubMacro() argument
1688 if (operand.IsZero() && rd.Is(rn) && rd.Is64Bits() && rn.Is64Bits() && in AddSubMacro()
1695 (rn.IsZero() && !operand.IsShiftedRegister()) || in AddSubMacro()
1698 Register temp = temps.AcquireSameSizeAs(rn); in AddSubMacro()
1709 } else if (rn.IsSP()) { in AddSubMacro()
1715 AddSub(rd, rn, imm_operand, S, op); in AddSubMacro()
1718 AddSub(rd, rn, temp, S, op); in AddSubMacro()
1721 AddSub(rd, rn, operand, S, op); in AddSubMacro()
1727 const Register& rn, in Adc() argument
1730 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC); in Adc()
1735 const Register& rn, in Adcs() argument
1738 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC); in Adcs()
1743 const Register& rn, in Sbc() argument
1746 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC); in Sbc()
1751 const Register& rn, in Sbcs() argument
1754 AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC); in Sbcs()
1773 const Register& rn, in AddSubWithCarryMacro() argument
1777 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in AddSubWithCarryMacro()
1787 Register temp = temps.AcquireSameSizeAs(rn); in AddSubWithCarryMacro()
1789 AddSubWithCarry(rd, rn, Operand(temp), S, op); in AddSubWithCarryMacro()
1798 Register temp = temps.AcquireSameSizeAs(rn); in AddSubWithCarryMacro()
1803 AddSubWithCarry(rd, rn, Operand(temp), S, op); in AddSubWithCarryMacro()
1814 Register temp = temps.AcquireSameSizeAs(rn); in AddSubWithCarryMacro()
1819 AddSubWithCarry(rd, rn, Operand(temp), S, op); in AddSubWithCarryMacro()
1822 AddSubWithCarry(rd, rn, operand, S, op); in AddSubWithCarryMacro()